USB Controller Registers
11-10
Intel
82801BA ICH2 Datasheet
When the USB Host Controller is in Software Debug Mode (USBCMD Register bit 5=1), the
single stepping software debug operation is as follows:
To Enter Software Debug Mode:
1. HCD puts Host Controller in Stop state by setting the Run/Stop bit to 0.
2. HCD puts Host Controller in Debug Mode by setting the SWDBG bit to 1.
3. HCD sets up the correct command list and Start Of Frame value for starting point in the Frame
List Single Step Loop.
4. HCD sets Run/Stop bit to 1.
5. Host Controller executes next active TD, sets Run/Stop bit to 0, and stops.
6. HCD reads the USBCMD register to check if the single step execution is completed
(HCHalted=1).
7. HCD checks results of TD execution. Go to step 4 to execute next TD or step 8 to end
Software Debug mode.
8. HCD ends Software Debug mode by setting SWDBG bit to 0.
9. HCD sets up normal command list and Frame List table.
10. HCD sets Run/Stop bit to 1 to resume normal schedule execution.
In Software Debug mode, when the Run/Stop bit is set, the Host Controller starts. When a valid TD
is found, the Run/Stop bit is reset. When the TD is finished, the HCHalted bit in the USBSTS
register (bit 5) is set.
0
Run/Stop (RS)
—R/W.
When set to 1, the ICH2 proceeds with execution of the schedule. The ICH2
continues execution as long as this bit is set. When this bit is cleared, the ICH2 completes the
current transaction on the USB and then halts. The HC Halted bit in the status register indicates
when the Host Controller has finished the transaction and has entered the stopped state. The Host
Controller clears this bit when the following fatal errors occur: consistency check failure, PCI Bus
errors.
1 = Run
0 = Stop
Table 11-3. Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation
SWDBG
(Bit 5)
Run/Stop
(Bit 0)
Description
0
0
If executing a command, the Host Controller completes the command and then
stops. The 1.0 ms frame counter is reset and command list execution resumes from
start of frame using the frame list pointer selected by the current value in the FRNUM
register. (While Run/Stop=0, the FRNUM register can be reprogrammed).
0
1
Execution of the command list resumes from Start Of Frame using the frame list
pointer selected by the current value in the FRNUM register. The Host Controller
remains running until the Run/Stop bit is cleared (by software or hardware).
1
0
If executing a command, the Host Controller completes the command and then stops
and the 1.0 ms frame counter is frozen at its current value. All status are preserved.
The Host Controller begins execution of the command list from where it left off when
the Run/Stop bit is set.
1
1
Execution of the command list resumes from where the previous execution stopped.
The Run/Stop bit is set to 0 by the Host Controller when a TD is being fetched. This
causes the Host Controller to stop again after the execution of the TD (single step).
When the Host Controller has completed execution, the HC Halted bit in the Status
Register is set.
Bit
Description
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