I/O Register Index
A-2
Intel
82801BA ICH2 Datasheet
Master PIC ICW2 Init. Cmd Word 2
Register
Master PIC ICW3 Init. Cmd Word 3
Register
Master PIC ICW4 Init. Cmd Word 4
Register
Master PIC OCW1 Op Ctrl Word 1
Register
21h
Section 9.4.3, “ICW2—Initialization Command Word 2
Register” on page 9-35
Section 9.4.4, “ICW3—Master Controller Initialization
Command Word 3 Register” on page 9-35
Section 9.4.6, “ICW4—Initialization Command Word 4
Register” on page 9-36
Section 9.4.7, “OCW1—Operational Control Word 1
(Interrupt Mask) Register” on page 9-36
Aliased at 20h–21h
24h–25h
Aliased at 20h–21h
28h–29h
Aliased at 20h–21h
24h–25h
Aliased at 20h–21h
2Ch–2Dh
Aliased at 20h–21h
30h–31h
Aliased at 20h–21h
34h–35h
Aliased at 20h–21h
38h–39h
Aliased at 20h–21h
3Ch–3Dh
Counter 0 Interval Time Status Byte
Format
Counter 0 Counter Access Port
Register
40h
Section 9.3.2, “SBYTE_FMT—Interval Timer Status
Byte Format Register” on page 9-32
Section 9.3.3, “Counter Access Ports Register” on
page 9-32
Counter 1 Interval Time Status Byte
Format
Counter 1 Counter Access Port
Register
41h
Section 9.3.2, “SBYTE_FMT—Interval Timer Status
Byte Format Register” on page 9-32
Section 9.3.3, “Counter Access Ports Register” on
page 9-32
Counter 2 Interval Time Status Byte
Format
Counter 2 Counter Access Port
Register
42h
Section 9.3.2, “SBYTE_FMT—Interval Timer Status
Byte Format Register” on page 9-32
Section 9.3.3, “Counter Access Ports Register” on
page 9-32
Timer Control Word Register
Timer Control Word Register Read
Back
Counter Latch Command
43h
Section 9.3.1, “TCW—Timer Control Word Register” on
page 9-30
Section 9.3.1.1, “RDBK_CMD—Read Back Command”
on page 9-31
Section 9.3.1.2, “LTCH_CMD—Counter Latch
Command” on page 9-31
Aliased at 40h–43h
50h–53h
NMI Status and Control Register
61h
Section 9.7.1, “NMI_SC—NMI Status and Control
Register” on page 9-51
NMI Enable Register
70h
Section 9.7.2, “NMI_EN—NMI Enable (and Real Time
Clock Index)” on page 9-52
Real-Time Clock (Standard RAM)
Index Register
70h
Table 9-7 “RTC (Standard) RAM Bank” on page 9-47
Section 9.7.2, “NMI_EN—NMI Enable (and Real Time
Clock Index)” on page 9-52
Real-Time Clock (Standard RAM)
Target Register
71h
Table 9-7 “RTC (Standard) RAM Bank” on page 9-47
Extended RAM Index Register
72h
Extended RAM Target Register
73h
Table A-1. ICH2 Fixed I/O Registers (Continued)
Register Name
Port
EDS Section and Location
Powered by ICminer.com Electronic-Library Service CopyRight 2003