Functional Description
5-4
Intel
82801BA ICH2 Datasheet
5.1.5
Parity Error Detection
The ICH2 can detect and report different parity errors in the system. The ICH2 can be programmed
to cause an NMI (or SMI# if NMI is routed to SMI#) based on detecting a parity error. The
conceptual logic diagram in
Figure 5-3
details all the parity errors that the ICH2 can detect, along
with their respective enable bits, status bits, and the results.
Note:
If NMIs are enabled and parity error checking on PCI is also enabled, then parity errors cause an
NMI. Some operating systems will not attempt to recover from this NMI, since it considers the
detection of a PCI error to be a catastrophic event.
5.1.6
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based “configuration space” that allows each device to contain up to 8
functions with each function containing up to 256 8-bit configuration registers. The PCI
specification defines two bus cycles to access the PCI configuration space: Configuration Read and
Configuration Write. Memory and I/O spaces are supported directly by the processor.
Configuration space is supported by a mapping mechanism implemented within the ICH2. The PCI
specification defines two mechanisms to access configuration space (Mechanism #1 and
Mechanism #2). The ICH2 only supports Mechanism #1.
Configuration cycles for PCI Bus #0 devices #2 through #31, and for PCI Bus numbers greater than
0 will be sent towards the ICH2 from the host controller. The ICH2 compares the non-zero Bus
Number with the Secondary Bus Number and Subordinate Bus number registers of its P2P bridge
to determine if the configuration cycle is meant for Primary PCI or a downstream PCI bus.
Type 0 to Type 0 Forwarding
When a Type 0 configuration cycle is received on the hub interface, the ICH2 forwards these
cycles to PCI and then reclaims them. The ICH2 uses address bits AD[15:14] to communicate the
ICH2 device numbers in Type 0 configuration cycles. If the Type 0 cycle on the hub interface
specifies any device number other than 30 or 31, the ICH2 will not set any address bits in the range
AD[31:11] during the corresponding transaction on PCI.
Table 5-1
shows the device number
translation.
The ICH2 logic generates single DWord configuration read and write cycles on the PCI bus. The
ICH2 generates a Type 0 configuration cycle for configurations to the bus number matching the
PCI bus. Type 1 configuration cycles are converted to Type 0 cycles in this case. If the cycle is
targeting a device behind an external bridge, the ICH2 runs a Type 1 cycle on the PCI bus.
Table 5-1. Type 0 Configuration Cycle Device Number Translation
Device # In Hub Interface Type 0
Cycle
AD[31:11] During Address Phase of Type 0 Cycle on PCI
0 through 29
0000000000000000_00000b
30
0000000000000000_01000b
31
0000000000000000_10000b
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