參數(shù)資料
型號： 82845MZ
廠商： INTEL CORP
元件分類： 外設(shè)及接口
英文描述： Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
中文描述： MULTIFUNCTION PERIPHERAL, PBGA593
封裝： 37.50 X 37.50 MM, FCBGA-593
文件頁數(shù)： 23/157頁
文件大?。?/td> 1407K
代理商： 82845MZ
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
250687-002
Datasheet
23
R
2.2.
DDR Interface
Table 5. DDR Interface Signal Descriptions
Signal Name
Type
Description
SCS#[3:0]
O
CMOS
Chip Select:
These pins select the particular DDR components during the active
state.
Note:
There is one SCS# per DDR-SDRAM Physical SO-DIMM device row. These
signals can be toggled on every rising System Memory Clock edge.
SMA[12:0]
O
CMOS
Multiplexed Memory Address:
These signals are used to provide the multiplexed
row and column address to DDR.
SBS[1:0]
O
CMOS
Memory Bank Address:
These signals define the banks that are selected within
each DDR row. The SMA and SBS signals combine to address every possible
location within a DDR device.
SRAS#
O
CMOS
DDR Row Address Strobe:
SRAS# may be heavily loaded and requires 2 DDR
clock cycles for setup time to the DDRs:
Used with SCAS# and SWE# (along with
SCS#) to define the DRAM commands.
SCAS#
O
CMOS
DDR Column Address Strobe:
SCAS# may be heavily loaded and requires 2 DDR
clock cycles for setup time to the DDRs. Used with SRAS# and SWE# (along with
SCS#) to define the DRAM commands.
SWE#
I/O
CMOS
Write Enable:
Used with SCAS# and SRAS# (along with SCS#) to define the
DRAM commands. SWE# is asserted during writes to DDR. SWE# may be heavily
loaded and requires 2 DDR clock cycles for setup time to the DDRs.
SDQ[63:0]
I/O
CMOS 2X
Data Lines:
These signals are used to interface to the DDR data bus.
SCB[7:0]
I/O
CMOS 2X
Data Lines:
These signals are used to interface to the SDRAM ECC signals (to be
used if SO-DIMMs support ECC).
SDQS[8:0]
I/O
CMOS
Data Strobes:
There is an associated data strobe (DQS) for each data strobe (DQ) and check
bit (CB) group.
SDQS8
-
> SCB[7:0]
SDQS7 -> SDQ[63:56]
SDQS6 -> SDQ[55:48]
SDQS5 -> SDQ[47:40]
SDQS4 -> SDQ[39:32]
SDQS3 -> SDQ[31:24]
SDQS2 -> SDQ[23:16]
SDQS1 -> SDQ[15:8]
SDQS0 -> SDQ[7:0]
SCKE[3:0]
O
CMOS
Clock Enable:
These pins are used to signal a self-refresh or power down
command to a DDR array when entering system suspend. SCKE is also used to
dynamically power down inactive DDR rows. There is one SCKE per DDR row.
These signals can be toggled on every rising SCLK edge.
RCVENOUT#
O
CMOS
Clock Output:
Used to emulate source-synch clocking for reads. Connects to
RCVENIN#.
RCVENIN#
I
CMOS
Clock Input:
Used to emulate source-synch clocking for reads. Connects to
RCVENOUT#.
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