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參數(shù)資料
| 型號： | 82845MZ |
| 廠商： | INTEL CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PBGA593 |
| 封裝： | 37.50 X 37.50 MM, FCBGA-593 |
| 文件頁數(shù)： | 82/157頁 |
| 文件大?。?/td> | 1407K |
| 代理商： | 82845MZ |
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Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
82
Datasheet
250687-002
R
3.7.36.
ERRCMD – Error Command Register – Device #0
Address Offset:
Default Value:
Access:
Size:
CA-CBh
0000h
Read Only, Read/Write
16 bits
This register enables various errors to generate an SERR message via the hub interface A. Since the
MCH-M does not have an SERR# signal, SERR messages are passed from the MCH-M to the ICH3-M
over the hub interface. When a bit in this register is set, an SERR message will be generated on hub
interface whenever the corresponding flag is set in the ERRSTS register. The actual generation of the
SERR message is globally enabled for Device #0 via the PCI Command register.
Note:
An error can generate one and only one error message via the hub interface A. It is software’s
responsibility to make sure that when an SERR error message is enabled for an error condition; SMI and
SCI error messages are disabled for that same error condition.
Bit
Description
15:10
Reserved
9
SERR on Non-DRAM Lock (LCKERR):
When this bit is asserted, the MCH-M will generate a hub
interface A SERR special cycle whenever a processor lock cycle is detected that does not hit DRAM
8:7
Reserved
6
SERR on Target Abort on hub interface A Exception (TAHLA_SERR):
When this bit is set, the
generation of the hub interface A SERR message is enabled when an MCH-M originated hub
interface A cycle is completed with “Target Abort” completion packet or special cycle status.
5
SERR on Detecting Hub Interface A Unimplemented Special Cycle (HIAUSCERR):
When this bit
is set to 1 the MCH-M generates an SERR message over hub interface A when an Unimplemented
Special Cycle is received on the hub interface. When this bit is set to 0 the MCH-M does not generate
an SERR message for this event. SERR messaging for Device 0 is globally enabled in the PCICMD
register.
4
SERR on AGP Access Outside of Graphics Aperture (OOGF_SERR):
When this bit is set, the
generation of the hub interface A SERR message is enabled when an AGP access occurs to an
address outside of the graphics aperture.
3
SERR on Invalid AGP Access (IAAF_SERR):
When this bit is set, the generation of the hub
interface A SERR message is enabled when an AGP access occurs to an address outside of the
graphics aperture and either to the 640K - 1M range or above the top of memory.
2
SERR on Invalid Translation Table Entry (ITTEF_SERR):
When this bit is set, the generation of the
hub interface A SERR message is enabled when an invalid translation table entry was returned in
response to an AGP access to the graphics aperture.
1
SERR Multiple-Bit DRAM ECC Error (DMERR_SERR):
When this bit is set, the generation of the
hub interface A SERR message is enabled when the MCH-M DRAM controller detects a multiple-bit
error. For systems not supporting ECC this bit must be disabled.
0
SERR on Single-bit ECC Error (DSERR):
When this bit is set, the generation of the hub interface A
SERR message is enabled when the MCH-M DRAM controller detects a single bit error. For systems
that do not support ECC this bit must be disabled.
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