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參數(shù)資料
| 型號： | 82845MZ |
| 廠商： | INTEL CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PBGA593 |
| 封裝： | 37.50 X 37.50 MM, FCBGA-593 |
| 文件頁數(shù)： | 37/157頁 |
| 文件大?。?/td> | 1407K |
| 代理商： | 82845MZ |
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Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
250687-002
Datasheet
37
R
The configuration access mechanism makes use of the CONFIG_ADDRESS Register (at I/O address
0CF8h though 0CFBh) and CONFIG_DATA Register (at I/O address 0CFCh though 0CFFh). To
reference a configuration register a Dword I/O write cycle is used to place a value into
CONFIG_ADDRESS that specifies the PCI bus, the device on that bus, the function within the device,
and a specific configuration register of the device function being accessed. CONFIG_ADDRESS[31]
must be 1 to enable a configuration cycle. CONFIG_DATA then becomes a window into the four bytes
of configuration space specified by the contents of CONFIG_ADDRESS. Any read or write to
CONFIG_DATA will result in the MCH-M translating the CONFIG_ADDRESS into the appropriate
configuration cycle.
The MCH-M is responsible for translating and routing the CPU’s I/O accesses to the
CONFIG_ADDRESS and CONFIG_DATA registers to internal MCH-M configuration registers, hub
interface, or AGP.
3.3.
Routing Configuration Accesses
The MCH-M supports two bus interfaces: the hub interface and AGP. PCI configuration cycles are
selectively routed to one of these interfaces. The MCH-M is responsible for routing PCI configuration
cycles to the proper interface. PCI configuration cycles to the ICH3-M internal devices, and Primary PCI
(including downstream devices) are routed to the ICH3-M via the hub interface. AGP configuration
cycles are routed to AGP. The AGP interface is treated as a separate PCI bus from the configuration
point of view. Routing of configuration AGP is controlled via the standard PCI-PCI bridge mechanism
using information contained within the PRIMARY BUS NUMBER, the SECONDARY BUS NUMBER,
and the SUBORDINATE BUS NUMBER registers of the corresponding PCI-PCI bridge device.
A detailed description of the mechanism for translating CPU I/O bus cycles to configuration cycles on
one of the buses is described below.
3.3.1.
PCI Bus #0 Configuration Mechanism
The MCH-M decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the configuration
cycle is targeting a PCI Bus #0 device.
The Host-HI Bridge entity within the MCH-M is hardwired as Device #0 on PCI Bus #0.
The Host-AGP Bridge entity within the MCH-M is hardwired as Device #1 on PCI Bus #0.
Configuration cycles to any of the MCH-M’s internal devices are confined to the MCH-M and not sent
over hub interface. Accesses to disabled MCH-M internal devices will be forwarded over the hub
interface as Type0 Configuration Cycles.
3.3.2.
Primary PCI and Downstream Configuration Mechanism
If the Bus Number in the CONFIG_ADDRESS is non-zero, and is less than the value in the Host-AGP
device’s SECONDARY BUS NUMBER register, or greater than the value in the Host-AGP device’s
SUBORDINATE BUS NUMBER register, the MCH-M will generate a Type 1 hub interface
Configuration Cycle. The ICH3-M compares the non-zero Bus Number with the SECONDARY BUS
NUMBER and SUBORDINATE BUS NUMBER registers of its P2P bridges to determine if the
configuration cycle is meant for Primary PCI or a downstream PCI bus.
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