參數資料
型號： 82845MZ
廠商： INTEL CORP
元件分類： 外設及接口
英文描述： Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
中文描述： MULTIFUNCTION PERIPHERAL, PBGA593
封裝： 37.50 X 37.50 MM, FCBGA-593
文件頁數： 80/157頁
文件大小： 1407K
代理商： 82845MZ
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
80
Datasheet
250687-002
R
3.7.34.
MCH-MCFG – MCH-M Configuration Register – Device #0
Offset:
Default:
Access:
Size:
C6-C7h
0000h
Read/Write Once, Read/Write, Read Only
16 bits
Bit
Description
15:12
Reserved
11
System Memory Frequency Select:
This bit must be programmed prior to memory initialization.
This bit
must
be programmed/set to “0” prior to memory initialization in order to guarantee proper
operation of the Intel845MZ.
0: System Memory frequency is set to 100 MHz
1: System Memory frequency is set to 133 MHz (845MP only)
10:6
Reserved
5
Monochrome Display adapter Present (MDAP):
This bit works with the VGA Enable bit in the
BCTRL register of device 1 to control the routing of host initiated transactions targeting MDA
compatible I/O and memory address ranges. This bit should not be set when the VGA Enable bit is
not set in device 1 BCTRL1 register. When the MDAP bit is set, accesses to MDA resources are
forwarded to hub interface A. MDA resources are defined as the following:
Memory addresses: 0B0000h - 0B7FFFh
I/O addresses: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, and 3BFh,
including ISA address aliases, (A[15:10] are not used in decode)
Any I/O reference that includes the I/O locations listed above, or their aliases, will be forwarded to the
hub interface A even if the reference also includes I/O locations not listed above.
Please refer to the System Address Map section of this document for further information.
4:3
Reserved
2
In-Order Queue Depth (IOQD):
This bit reflects the value sampled on HA[7]# on the deassertion of
the CPURST#. It indicates the depth of the host bus in-order queue (i.e. level of host bus pipelining).
If IOQD is set to 1 (HA[7]# sampled “1” i.e. undriven on the host bus), then the depth of the host bus
in-order queue is configured to the maximum allowed by the host bus protocol (i.e. 12). Note that the
MCH-M has an 12 deep IOQ and will assert BNR# on the bus to limit the number of queued bus
transactions to 12. If the IOQD bit is set to 0 (HA[7]# is sampled asserted , i.e., “0”), then depth of
the host bus in-order queue is set to 1 (i.e. no pipelining support on the host bus).
Note that HA[7]# is not driven by the MCH-M during CPURST#. If an IOQ size of 1 is desired, HA[7]#
must be driven low during CPURST# by an external source.
1
Reserved
0
Reserved
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