- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378217 > 82865G (Intel Corp.) Intel 865G/865GV Graphics and Memory Controller Hub PDF資料下載
參數(shù)資料
| 型號： | 82865G |
| 廠商： | Intel Corp. |
| 英文描述： | Intel 865G/865GV Graphics and Memory Controller Hub |
| 中文描述： | 英特爾865G/865GV圖形和內(nèi)存控制器中樞 |
| 文件頁數(shù)： | 15/249頁 |
| 文件大?。?/td> | 3540K |
| 代理商： | 82865G |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁
16
Intel
82865G/82865GV GMCH Datasheet
Introduction
1.1
Terminology
This section provides the definitions of some of the terms used in this document.
Table 1. General Terminology (Sheet 1 of 2)
Terminology
Description
AGP
Accelerated Graphics Port. In this document AGP refers to the AGP/PCI interface that is in
the GMCH. The GMCH AGP interface supports only 0.8 V/1.5 V AGP 2.0/AGP 3.0
compliant devices using PCI (66 MHz), AGP 1X (66 MHz), 4X (266 MHz), and
8X (533 MHz) transfers. GMCH does
not
support any 3.3 V devices. For AGP 2.0, PIPE#
and SBA addressing cycles and their associated data phases are generally referred to as
AGP transactions. FRAME# cycles are generally referred to as AGP/PCI transactions.
Bank
DRAM chips are divided into multiple banks internally. Commodity parts are all 4 bank,
which is the only type the GMCH supports. Each bank acts somewhat like a separate
DRAM, opening and closing pages independently, allowing different pages to be open in
each. Most commands to a DRAM target a specific bank, but some commands
(i.e., Precharge All) are targeted at all banks. Multiple banks allows higher performance by
interleaving the banks and reducing page miss cycles.
Channel
In the GMCH a DRAM channel is the set of signals that connect to one set of DRAM
DIMMs. The GMCH has two DRAM channels, (a pair of DIMMs added at a time, one on
each channel).
Chipset Core
The GMCH internal base logic.
Column
Address
The column address selects one DRAM location, or the starting location of a burst, from
within the open page on a read or write command.
Double-Sided
DIMM
Terminology often used to describe a DIMM that contains two DRAM rows. Generally, a
double-sided DIMM contains two rows, with the exception noted above. This terminology is
not used in this document.
DDR
Double Data Rate SDRAM. DDR describes the type of DRAMs that transfer two data items
per clock on each pin. This is the only type of DRAM supported by the GMCH.
Full Reset
A Full GMCH Reset is defined in this document when RSTIN# is asserted.
GART
Graphics Aperture Re-map Table. GART is a table in memory containing the page re-map
information used during AGP aperture address translations.
GMCH
Graphics and Memory Controller Hub. The GMCH component contains the processor
interface, SDRAM controller, AGP interface, CSA interface and an integrated 3D/2D/display
graphics core. It communicates with the I/O controller hub (Intel
ICH5) over a proprietary
interconnect called HI.
GTLB
Graphics Translation Look-aside Buffer. A cache used to store frequently used GART
entries.
Graphics Core
The internal graphics related logic in the GMCH.
HI
Hub Interface. HI is the proprietary hub interface that connects the GMCH to the ICH5. In
this document HI cycles originating from or destined for the primary PCI interface on the
ICH5 are generally referred to as HI/PCI or simply HI cycles.
Host
This term is used synonymously with processor.
Intel
ICH5
Fifth generation
IO Controller Hub component that contains additional functionality
compared to the ICH4.
IGD
Integrated Graphics Device. IGD refers to the graphics device integrated into the GMCH.
Primary PCI
The physical PCI bus that is driven directly by the ICH5 component. Communication
between PCI and the GMCH occurs over the hub interface. Note that even though the
Primary PCI bus is referred to as PCI, it is
not
PCI Bus 0 from a configuration standpoint.
FSB
Processor Front-Side Bus. This is the processor system bus.
Row
A group of DRAM chips that fill out the data bus width of the system and are accessed in
parallel by each DRAM command.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82865GV | Intel 865G/865GV Graphics and Memory Controller Hub |
| 8288 | Bus Controller for SAB 8086 Family Processors |
| 828 | 2 X 2 8-Pole Filters |
| 8291A | GPIB TALKER/LISTENER |
| 829B | SILICON 28V HYPERABRUPT VARACTOR DIODES |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82865GV | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 865G/865GV Graphics and Memory Controller Hub |
| 82865N | 功能描述:HEX DIE 5/8-11 制造商:apex tool group 系列:* 零件狀態(tài):在售 標準包裝:1 |
| 828661-1 | 功能描述:汽車連接器 25P JUN-TIMER CONN RoHS:否 制造商:Amphenol SINE Systems 產(chǎn)品:Contacts 系列:ATP 位置數(shù)量: 型式:Female 安裝風(fēng)格: 端接類型: 觸點電鍍:Nickel |
| 828662-1 | 制造商:TE Connectivity 功能描述:CONN TIMER CONN M 16 POS 5MM SLDR ST TH - Bulk 制造商:TE Connectivity 功能描述:16P JUN-TIMER STECK 制造商:TE Connectivity 功能描述:Conn Timer Connector M 16 POS 5mm Solder ST Thru-Hole |
| 82866N | 功能描述:HEX DIE 5/8-18 制造商:apex tool group 系列:* 零件狀態(tài):在售 標準包裝:1 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。