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48
Intel
82865G/82865GV GMCH Datasheet
Register Description
3.2
Platform Configuration Structure
In some previous chipsets, the GMCH and the I/O Controller Hub (ICHx) were physically
connected by PCI bus 0. From a configuration standpoint, both components appeared to be on PCI
bus 0, which was also the system’s primary PCI expansion bus. The GMCH contained two PCI
devices while the ICHx bridge was considered one PCI device with multiple functions.
In the 865G chipset platform, the configuration structure is significantly different. The GMCH and
the ICH5 are physically connected by a hub interface (HI); thus, from a configuration standpoint,
HI is logically PCI bus 0. As a result, all devices internal to the GMCH and ICH5 appear to be on
PCI bus 0. The system’s primary PCI expansion bus is physically attached to ICH5 and, from a
configuration perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI bridge;
therefore, it has a programmable PCI Bus number. Note that the primary PCI bus is referred to as
PCI_A in this document and is
not
PCI bus 0 from a configuration standpoint. The AGP appears to
system software to be a real PCI bus behind PCI-to-PCI bridges resident as devices on PCI bus 0.
The GMCH contains four PCI devices within a single physical component. The configuration
registers for the four devices are mapped as devices residing on PCI bus 0.
Device 0:
Host-HI Bridge/DRAM Controller. Logically this appears as a PCI device residing
on PCI bus 0. Physically, Device 0 contains the standard PCI registers, SDRAM registers, the
Graphics Aperture controller, configuration for HI, and other GMCH specific registers.
Device 1:
Host-AGP Bridge. Logically this appears as a “virtual” PCI-to-PCI bridge residing
on PCI bus 0. Physically, Device 1 contains the standard PCI-to-PCI bridge registers and the
standard AGP/PCI configuration registers (including the AGP I/O and memory address
mapping).
Device 2:
Integrated Graphics Controller. Logically this appears as a PCI device residing on
PCI bus 0. Physically, Device 2 contains the configuration registers for 3D, 2D, and display
functions.
Device 3:
Communications Streaming Architecture (CSA) Port. Appears as a virtual PCI-CSA
(PCI-to-PCI) bridge device
Device 6:
Function 0: Overflow Device. The sole purpose of this device is to provide
additional configuration register space for Device 0.
Reserved
Registers
In addition to reserved bits within a register, the GMCH contains address locations in the
configuration space of the Host-HI Bridge entity that are marked either “Reserved” or
“Intel Reserved”. The GMCH responds to accesses to reserved address locations by
completing the host cycle. When a reserved register location is read, a zero value is
returned. (reserved registers can be 8, 16, or 32 bits in size). Writes to reserved registers
have no effect on the GMCH.
Caution:
Register locations that are marked as “Intel Reserved” must
not
be modified
by system software. Writes to “Intel Reserved” register locations may cause
system failure. Reads to “Intel Reserved” register locations may return a non-
zero value.
Default Value
upon a Reset
Upon a reset, the GMCH sets all of its internal configuration registers to predetermined
default states. Some register values at reset are determined by external strapping
options. The default state represents the minimum functionality feature set required to
successfully bring up the system. Hence, it does not represent the optimal system
configuration. It is the responsibility of the system initialization software (usually BIOS) to
properly determine the SDRAM configurations, operating parameters and optional
system features that are applicable, and to program the GMCH registers accordingly.
Term
Description