參數(shù)資料
型號(hào)： 82865G
廠商： Intel Corp.
英文描述： Intel 865G/865GV Graphics and Memory Controller Hub
中文描述： 英特爾865G/865GV圖形和內(nèi)存控制器中樞
文件頁(yè)數(shù)： 36/249頁(yè)
文件大?。?/td> 3540K
代理商： 82865G
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Intel
82865G/82865GV GMCH Datasheet
37
Signal Description
NOTES:
1. PCIRST# from the ICH5 is connected to RSTIN# and is used to reset AGP interface logic in the GMCH. The
AGP agent will also typically use PCIRST# provided by the ICH5 as an input to reset its internal logic.
2. LOCK# signal is
not
supported on the AGP interface (even for PCI operations).
3. The term
(2.0)
following a signal name indicates its function in AGP 2.0 signaling mode (1.5 V swing).
4. The term
(3.0)
following a signal name indicates its function in AGP 3.0 signaling mode (0.8 V swing).
2.5.5.1
PCI Pins during PCI Transactions on AGP Interface
PCI signals described in a previous table behave according to PCI 2.1 specifications when used to
perform PCI transactions on the AGP interface.
2.5.6
Multiplexed Intel
DVOs on AGP
The following signals are multiplexed on the AGP signals.
GC/BE[3:0]#
(2.0
)
GC#/BE[3:0]
(3.0)
I/O
AGP
Command/Byte Enables:
These signals provide the command during the
address phase of a GFRAME(#) or GPIPE(#) transaction and byte enables
during data phases. Byte enables are not used for read data of AGP 1X and
2X and 4X and 8X reads. These signals operate at the same data rate as the
GAD[31:0] signals at any given time.
GPAR/
ADD_DETECT
I/O
AGP
Parity:
GPAR is not used on AGP transactions. It is used during GFRAME(#)
based transactions as defined by the PCI specification. GPAR is not used
during fast writes.
Add Detect:
The GMCH multiplexes an ADD_DETECT signal with the GPAR
signal on the AGP bus. This signal acts as a strap and indicates whether the
interface is in AGP or DVO mode. The GMCH has an internal pull-up on this
signal that will naturally pull it high. If an ADD card is present, the signal will be
pulled low on the ADD card and the AGP/DVO multiplex select bit in the
GMCHCFG register will be set to DVO mode. Motherboards that do not use an
AGP connector should have a pull-down resistor on ADD_DETECT if they
have digital display devices connected to the interface.
DBI_LO
(3.0 only)
I/O
AGP
Dynamic Bus Inversion LO:
This AGP 3.0 only signal goes along with
GAD[15:0] to indicate whether GAD[15:0] must be inverted on the receiving
end.
DBI_LO= 0: GAD[15:0] are not inverted so receiver may use as is.
DBI_LO= 1: GAD[15:0] are inverted so receiver must invert before use.
The GADSTBF1 and GADSTBS1 strobes are used with the DBI_LO. Dynamic
bus inversion is used in AGP 3.0 signaling mode only.
Signal Name
Type
Description
Signal Name
Type
Description
DVOB_CLK;
DVOB_CLK#
O
AGP
DVOB Clock Output:
These pins provide a differential pair reference clock
that can run up to 165 MHz. Care should be taken to be sure that DVOB_CLK
is connected to the primary clock receiver of the Intel
DVO device.
DVOB_D[11:0]
O
AGP
DVOB Data:
This data bus is used to drive 12-bit pixel data on each edge of
DVOB_CLK(#). This provides 24-bits of data per clock.
DVOB_HSYNC
O
AGP
Horizontal Sync:
HSYNC signal for the DVOB interface. The active polarity
of the signal is programmable.
DVOB_VSYNC
O
AGP
Vertical Sync:
VSYNC signal for the DVOB interface. The active polarity of
the signal is programmable.
DVOB_BLANK#
O
AGP
Flicker Blank or Border Period Indication:
DVOB_BLANK# is a
programmable output pin driven by the GMCH. When programmed as a blank
period indication, this pin indicates active pixels excluding the border. When
programmed as a border period indication, this pin indicates active pixel
including the border pixels.
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