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Intel
82865G/82865GV GMCH Datasheet
21
Introduction
Single-Channel DDR Configuration
Up to 4.0 GB of DDR
Supports up to four DDR DIMMs (2 DIMMs per channel), single-sided and/or double-sided
Supports DDR266, DDR333, and DDR400 unregistered non-ECC DIMMs
Supports up to 32 simultaneous open pages
Does not support mixed-mode / uneven double-sided DDR DIMMs
Dual-Channel DDR Configuration - Lockstep
Up to 4.0 GB of DDR
Supports up to four DDR DIMMs, single-sided and/or double-sided
DIMMS must be populated in identical pairs for dual-channel operation
Supports 16 simultaneous open pages (four per row)
Supports DDR266, DDR333, and DDR400 unregistered non-ECC DIMMs
1.4.3
Hub Interface
Communication between the GMCH and the ICH5 occurs over the hub interface. The GMCH
supports HI 1.5 that uses HI 1.0 protocol with HI 2.0 electrical characteristics. The hub interface
runs at 266 MT/s (with 66 MHz base clock) and uses 1.5 V signaling. Acceses between hub
interface and AGP/PCI_B are limited to hub interface-originated memory writes to AGP.
1.4.4
Communications Streaming Architecture (CSA) Interface
The CSA interface connects the GMCH with a Gigabit Ethernet (GbE) controller. The GMCH
supports HI 1.5 over the interface that uses HI 1.0 protocol with HI 2.0 electrical characteristics.
The CSA interface runs at 266 MT/s (with 66 MHz base clock) and uses 1.5 V signaling.
1.4.5
Multiplexed AGP and Intel
DVO Interface
The GMCH multiplexes an AGP interface with two Intel
DVOs ports.
AGP Interface
A single AGP or PCI 66 component or connector (not both) is supported by the GMCH’s AGP
interface. Support for AGP 3.0 includes 0.8 V and 1.5 V AGP electrical characteristics. Support for
a single PCI-66 device is limited to the subset supported by the AGP 2.0 specification. An external
graphics accelerator is not a requirement due to the GMCH’s integrated graphics capabilities. The
BIOS will disable the IGD if an external AGP device is detected. The AGP PCI_B buffers operate
only in the 1.5 V mode and support the AGP 1.5 V connector.
The AGP/PCI_B interface supports up to 8X AGP signaling and up to 8X Fast Writes. AGP
semantic cycles to system DDR are not snooped on the host bus. PCI semantic cycles to system
DDR are snooped on the host bus. The GMCH supports PIPE# or SBA[7:0] AGP address
mechanisms, but not both simultaneously. Either the PIPE# or the SBA[7:0] mechanism must be
selected during system initialization. The GMCH contains a 32 deep AGP request queue. High-
priority accesses are supported.