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Intel
82865G/82865GV GMCH Datasheet
47
Register Description
Register Description
3
The GMCH contains two sets of software accessible registers, accessed via the host processor I/O
address space:
Control registers that are I/O mapped into the processor I/O space control access to PCI and
AGP configuration space.
Internal configuration registers residing within the GMCH are partitioned into three logical
device register rests (“l(fā)ogical” since they reside within a single physical device). The first
register set is dedicated to Host-Hub Interface functionality (controls PCI bus #0 operations
including DRAM configuration, other chipset operating parameters, and optional features).
The second register block is dedicated to Host-AGP/PCI_B Bridge functions (controls AGP/
PCI_B interface configurations and operating parameters). The third register block is
dedicated to the Integrated Graphics Device (IGD).
This configuration scheme is necessary to accommodate the existing and future software
configuration model supported by Microsoft where the host bridge functionality will be supported
and controlled via dedicated and specific driver and virtual PCI-to-PCI bridge functionality will be
supported via standard PCI bus enumeration configuration software. The term “virtual” is used to
designate that no real physical embodiment of the PCI-to-PCI bridge functionality exists within the
GMCH, but that GMCH’s internal configuration register sets are organized in this particular
manner to create that impression to the standard configuration software.
The GMCH supports PCI configuration space accesses using the mechanism denoted as
Configuration Mechanism 1 in the PCI specification. The GMCH internal registers (both I/O
mapped and configuration registers) are accessible by the host processor. The registers can be
accessed as Byte, Word (16-bit), or DWord (32-bit) quantities, with the exception of
CONFIG_ADDRESS which can only be accessed as a DWord. All multi-byte numeric fields use
“l(fā)ittle-endian” ordering (i.e., lower addresses contain the least significant parts of the field).
3.1
Register Terminology
Term
Description
RO
Read Only
. If a register is read only, writes to this register have no effect.
R/W
Read/Write
. A register with this attribute can be read and written.
R/W/L
Read/Write/Lock
. A register with this attribute can be read, written, and Locked.
R/WC
Read/Write Clear
. A register bit with this attribute can be read and written. However, a
write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect.
R/WO
Read/Write Once.
A register bit with this attribute can be written to only once after power
up. After the first write, the bit becomes read only.
L
Lock.
A register bit with this attribute becomes Read Only after a lock bit is set.
Reserved Bits
Some of the GMCH registers described in this section contain reserved bits. These bits
are labeled “Reserved”. Software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined bits and not rely on
reserved bits being any particular value. On writes, software must ensure that the values
of reserved bit positions are preserved. That is, the values of reserved bit positions must
first be read, merged with the new values for other bit positions and then written back.
Note that software does not need to perform a read-merge-write operation for the
Configuration Address (CONFIG_ADDRESS) register.