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參數(shù)資料
| 型號(hào)： | 82865GV |
| 廠商： | Intel Corp. |
| 英文描述： | Intel 865G/865GV Graphics and Memory Controller Hub |
| 中文描述： | 英特爾865G/865GV圖形和內(nèi)存控制器中樞 |
| 文件頁(yè)數(shù)： | 32/249頁(yè) |
| 文件大?。?/td> | 3540K |
| 代理商： | 82865GV |
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Intel
82865G/82865GV GMCH Datasheet
33
Signal Description
2.5
AGP Interface
2.5.1
AGP Addressing Signals
NOTES:
1. The table contains two mechanisms to queue requests by the AGP master. Note that the master can only use
one mechanism. When
GPIPE#
is used to queue addresses the master is not allowed to queue addresses
using the SB bus. For example, during configuration time, if the master indicates that it can use either
mechanism, the configuration software will indicate which mechanism the master will use. Once this choice
has been made, the master will continue to use the mechanism selected until the master is reset (and
reprogrammed) to use the other mode. This change of modes is not a dynamic mechanism but rather a static
decision when the device is first being configured after reset.
2. The term
(2.0)
following a signal name indicates its function in AGP 2.0 signaling mode (1.5 V swing).
3. The term
(3.0)
following a signal name indicates its function in AGP 3.0 signaling mode (0.8 V swing).
Signal Name
Type
Description
GPIPE#
(2.0)
DBI_HI
(3.0)
I/O
AGP
Pipelined Read:
This signal
is asserted by the current master to indicate a full
width address is to be queued by the target. The master enqueues one request
each rising clock edge while GPIPE# is asserted. When GPIPE# is
deasserted, no new requests are enqueued across the GAD bus.
GPIPE# may be used in AGP 2.0 signaling modes, but is not permitted by the
AGP 3.0 specification. When operating in AGP 3.0 signaling mode, GPIPE# is
used for DBI_HI.
GPIPE# is a sustained tri-state signal from the master
(
graphics controller
)
and
is an input to the GMCH.
In AGP 3.0 signaling mode this signal is Dynamic Bus Inversion HI.
Dynamic Bus Inversion HI
: This signal goes along with GAD[31:16] to
indicate whether GAD[31:16] must be inverted on the receiving end.
DBI_HI = 0:
GAD[31:16] are not inverted so receiver may use as is.
DBI_HI = 1:
GAD[31:16] are inverted so receiver must invert before use.
The GADSTBF1 and GADSTBS1 strobes are used with DBI_HI. In AGP 3.0
4X data rate mode dynamic bus inversion is disabled by the GMCH while
transmitting (data never inverted and BI_HI driven low); dynamic bus inversion
is enabled when receiving data. For 8X data rate, dynamic bus inversion is
enabled when transmitting and receiving data.
GSBA[7:0]
(2.0)
GSBA[7:0]#
(3.0)
I
AGP
Sideband Address:
This bus
provides an additional bus to pass address and
command to the GMCH from the AGP master.
NOTE:
In AGP 2.0 signaling mode, when sideband addressing is disabled,
these signals are isolated. When sideband addressing is enabled,
internal pull-ups are enabled to prevent indeterminate values on them
in cases where the Graphics Card may not have its GSBA[7:0] output
drivers enabled yet.
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| 82865N | 功能描述:HEX DIE 5/8-11 制造商:apex tool group 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:1 |
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