reading the Mode register location. A clear Mode Register Counter command is
provided to allow the CPU to restart the mode read process at a known point. During
mode read operation, bits 0 and 1 are one. Refer to Figure 8-3.
B7
B6
B5
B4
B3
B2
B1
B0
_________________
________ ________
_________________
_________________
CS<1:0> Channel Select
TT<1:0> Type of Transfer
AI
Auto-Initialization
DEC
Address Counter Direction
M<1:0> Mode Selection
bits:
B0-B1
CS<1:0>
Channel Select bits 1 and 0 determine the channel for which the
Mode register is written. Read back of a Mode register results in bits
1 and 0 both being ones. Channel Select is as follows:
Channel 0 Select
when CS1 = 0 and CS0 = 0
Channel 1 Select
when CS1 = 0 and CS0 = 1
Channel 2 Select
when CS1 = 1 and CS0 = 0
Channel 3 Select
when CS1 = 1 and CS0 = 1
Bits 2 and 3 control the type of transfer that is to be performed. The
type of transfer is as follows:
Verify Transfer
when TT1 = 0 and TT0 = 0
Write Transfer
when TT1 = 0 and TT0 = 1
Read Transfer
when TT1 = 1 and TT0 = 0
Illegal
when TT1 = 1 and TT0 = 1
The Auto-Initialization function is enabled by writing a one in bit 4
of the Mode register.
Determines direction of the address counter. A one in bit 5
decrements the address after each transfer.
Mode selection for each channel is accomplished by bit 6 and 7. The
type of modes are as follows:
Demand Mode
when M1 = 0 and M0 = 0
Single Cycle Mode
when M1 = 0 and M0 = 1
Block Mode
when M1 = 1 and M0 = 0
Cascade Mode
when M1 = 1 and M0 = 1
B2-B3
TT<1:0>
B4
AI
B5
DEC
B6-B7
M<1:0>
Figure 8-3.
Mode Register
DMA Controller
DMA Register Descriptions
I
Chips and Technologies, Inc.
P R E L I M I N A R Y
Revision 3.0
8-11