- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376472 > 82C836A-16 (Electronic Theatre Controls, Inc.) Single-Chip 386sx AT PDF資料下載
參數(shù)資料
| 型號： | 82C836A-16 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single-Chip 386sx AT |
| 中文描述： | 單芯片386sx在 |
| 文件頁數(shù)： | 43/205頁 |
| 文件大?。?/td> | 3878K |
| 代理商： | 82C836A-16 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁當(dāng)前第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁
RAM that can be accessed instead of ROM in the 0C0000H-0FFFFFH range is called
shadow RAM. (RAM in the 0A0000H-0BFFFFH range is also referred to as shadow
RAM.) This feature is invoked by copying an image of the BIOS (which is in ROM)
into an area of RAM, thus allowing operating systems and software applications to make
faster accesses to the shadowed BIOS (rather than ROM which is much slower).
The degree of performance improvement derived from the use of shadow RAM depends
primarily on the difference in access times between ROM and DRAM cycles. At higher
system speeds, the difference can be significant. Additionally, shadow RAM maintains
maximum BIOS performance when using either a single 8-bit ROM (such as a 27512) or
two smaller 8-bit ROMs (for the same total ROM capacity). Using only one ROM
reduces component count and circuit board size.
The following procedure enables shadow RAM. The program that performs this
procedure must reside in RAM while it is executing, because ROM must be disabled
while writing to the shadow RAM area:
1.
2.
3.
4.
5.
6.
Disable interrupts.
Copy the ROM BIOS into RAM, below the start of ROM.
Disable -ROMCS using internal configuration register 48H.
Enable the shadow RAM using internal configuration registers 4AH-4CH.
Copy the BIOS from low DRAM into the area of memory allocated for shadow RAM.
If desired, the BIOS can be copied in several blocks by enabling -ROMCS or shadow
RAM as needed and repeating steps 2 through 5 for each block.
Make the shadow RAM read-only, using internal configuration register 49H.
Re-enable interrupts.
7.
8.
DRAM Interface
The 82C836B includes a DRAM controller that directly supports up to 16MB of memory
in four banks. The DRAM controller in the 82C836B is capable of operating in three
possible modes:
Multiple RAS Active (MRA), also known as dedicated CAS
In this mode, SCATsx provides four RAS signals and eight CAS signals for
controlling up to four DRAM banks, each bank 16-bits wide (plus two parity bits,
if desired). Each CAS signal is dedicated to controlling one eight-bit half of one
bank. Page interleaved access is used whenever possible, with up to four RAS
signals allowed to be active at the same time. The result is very high performance
in four-bank systems, since a high percentage of DRAM accesses can be CAS-only
zero wait-state accesses. MRA mode is recommended for all new designs, both for
performance reasons and to improve worst-case timing margins, particularly at
25MHz. The only disadvantage is that an external 74F153 and 74ALS138 are
needed to provide seven DREQ and DACK signals, see Figure 5-1.
I
DRAM Interface
System Interface
5-2
Revision 3.0
P R E L I M I N A R Y
Chips and Technologies, Inc.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82C836A-20 | Single-Chip 386sx AT |
| 82C836B | Single-Chip 386sx AT |
| 82C862 | FireLink USB Dual Controller Quad Port USB |
| 82C931 | Plug and Play Integrated Audio Controller |
| 82S09 | 576-BIT BIPOLAR RAM (64 X 9) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82C836A-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip 386sx AT |
| 82C836B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip 386sx AT |
| 82C83H | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Octal Latching Inverting Bus Driver |
| 82C84 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
| 82C84A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。