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參數(shù)資料
| 型號(hào)： | 82C836A-16 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single-Chip 386sx AT |
| 中文描述： | 單芯片386sx在 |
| 文件頁(yè)數(shù)： | 164/205頁(yè) |
| 文件大小： | 3878K |
| 代理商： | 82C836A-16 |
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The following programmable options are available with hidden refresh (ICR 63H):
RAS-only Refresh----In RAS-only refresh, -CAS remains high and -MWE remains low.
AT Refresh OFF----In this mode, ALE, -REF and -XMEMR remain inactive during
hidden refresh. IOCHRDY has no effect. Only the local DRAM is refreshed, not the
AT bus, and the total refresh cycle time is correspondingly shorter (see Table 11-1).
For compatibility with many AT bus add-in cards, AT refresh should not be turned off.
Refresh on Idle----Enabling this option prevents hidden refresh from starting until after
a CPU idle state. Normally, a hidden refresh can begin as early as the next T-state
following -READY, as shown in Figure 11-17. Refresh on idle prevents a hidden
refresh from starting if the next T-state after -READY is a T1-state (-ADS asserted).
In most systems, refresh on idle will probably have no measurable performance effect
and should remain disabled.
The exact number of PROCCLK cycles between various events in hidden refresh
depends on the CPU speed as programmed in ICR 63H. The PROCCLK counts also
depend on whether AT refresh is enabled or disabled, as in the following Table.
Table 11-2.
PROCCLK Cycles and Hidden Refresh
Events
16MHz
20MHz
25MHz
ALE rise to -REF/-CAS fall
2
2
2
2
2
2
-REF/-CAS fall to -XMEMR/-RAS fall
4
1
5
2
7
2
-XMEMR/-RAS fall to IOCHRDY sampling
2
----
3
----
4
----
IOCHRDY sampled high to -XMEMR/-RAS rise
5
----
6
----
7
----
Total -XMEMR/-RAS low time without IOCHRDY
7
4
9
4
11
4
-XMEMR/-RAS rise to -REF/-CAS rise
2
1
3
1
3
1
-REF/-CAS rise to ALE fall
4
4
4
5
4
5
Total hidden refresh time without IOCHRDY
20
12
24
14
28
14
Denotes AT refresh OFF.
Plus one PROCCLK if needed to make ALE fall at end of T-state.
Standby Refresh (32KHz-Based)
In addition to HLDA refresh (14.3MHz based, CAS-before-RAS or RAS-only)
and hidden refresh, the 82C836B also supports standby refresh (useful only in
CAS-before-RAS mode). Standby refresh operates only if it has been enabled via
ICR 60H. It allows the contents of DRAM to be preserved during power down.
Figure 11-18 shows standby refresh timing:
PWRGOOD going low indicates the imminent loss of main power. The 82C836
may complete one more normal refresh (HLDA or hidden), but must then switch to
standby refresh as quickly as possible.
I
CPU Access to AT-Bus
System Timing Relationships
11-32
Revision 3.0
P R E L I M I N A R Y
Chips and Technologies, Inc.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82C836A-20 | Single-Chip 386sx AT |
| 82C836B | Single-Chip 386sx AT |
| 82C862 | FireLink USB Dual Controller Quad Port USB |
| 82C931 | Plug and Play Integrated Audio Controller |
| 82S09 | 576-BIT BIPOLAR RAM (64 X 9) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82C836A-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip 386sx AT |
| 82C836B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip 386sx AT |
| 82C83H | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Octal Latching Inverting Bus Driver |
| 82C84 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
| 82C84A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
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