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參數(shù)資料
| 型號(hào)： | 82C836A-16 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single-Chip 386sx AT |
| 中文描述： | 單芯片386sx在 |
| 文件頁(yè)數(shù)： | 34/205頁(yè) |
| 文件大小： | 3878K |
| 代理商： | 82C836A-16 |
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The refresh interval during stand-by refresh is programmable: 15
μ
s, 122
μ
s, 244
μ
s,
or 488
μ
s between refreshes (.5, 2, 4, or 8 cycles of the 32.768KHz input frequency).
The Power Sense input (PS/MFP5) must remain high during power down in order for
stand-by refresh to work. A logic low level on PS while PWRGOOD is low will clear
the stand-by enable bit in ICR 60H. Since PWRGOOD is low, SCATsx will then
become fully reset.
During power-down stand-by refresh, the following output signals remain active
instead of becoming high impedance:
°
-CAS3, -CAS2, -CAS1 (if multiple RAS active mode is enabled). Refer to
Section
5, System Interface
, subsection titled
Memory Interface
for a detailed discussion of
the multiple RAS active mode and 4MB DRAM Configurations.
°
-CAS0, -MWE, -RAS0, -RAS1, -RAS2.
°
-RAS3 (if not using a 4MB DRAM configuration). Refer to
Section 5, System
Interface
, subsection titled
Memory Interface
for a detailed discussion of the
multiple RAS active mode and 4MB DRAM Configurations.
°
If a 4MB DRAM configuration is used, MA10 is actively driven to a continuous
logic high level.
°
MA0-9 are actively driven to a continuous logic high level.
°
OSC2 remains actively driven to a continuous logic low level; this is always the
case during power-down even if the Standby Refresh is disabled.
During normal powered-on operation, the 82C836B can optionally generate fast 8-bit
timing or true 16-bit cycles for video I/O and/or video memory accesses in selected
programmable address ranges (see ICR 61H and 62H). This capability is designed to
improve video performance in products that use on-board video subsystems, including
very compact laptop and notebook PC’s with 8-bit video interfaces.
Operational Power Management
Average system power consumption can be reduced by slowing or stopping the processor
clock during idle periods. If a nonstatic CPU is used, the processor clock can be slowed
down. If a static CPU is used, the processor clock can be stopped completely.
In the 82C836, ‘‘sleep’’ mode is provided in which a HALT instruction, executed by the
CPU, triggers the slowing or stopping of PROCCLK. The sleep mode is enabled by bit 7
in internal configuration register 46H, and bits 1 and 0 determine the frequency of
PROCCLK during sleep mode. The sleep frequency is selectable between 0 (PROCCLK
stopped), CXIN/2, CXIN/4 or CXIN/8.
I
Operational Power Management
Functional Description
3-6
Revision 3.0
P R E L I M I N A R Y
Chips and Technologies, Inc.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82C836A-20 | Single-Chip 386sx AT |
| 82C836B | Single-Chip 386sx AT |
| 82C862 | FireLink USB Dual Controller Quad Port USB |
| 82C931 | Plug and Play Integrated Audio Controller |
| 82S09 | 576-BIT BIPOLAR RAM (64 X 9) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82C836A-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip 386sx AT |
| 82C836B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip 386sx AT |
| 82C83H | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Octal Latching Inverting Bus Driver |
| 82C84 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
| 82C84A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
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