Refresh
The refresh timing specifications are shown in Tables 12-40 through 12-42
Table 12-40.
Refresh----Output Responses
Symbol
Parameters
Min.
Max.
t260
-REFRESH active from HLDA
----
71
t261
-REFRESH float from OSC2 rise
----
55
t262
Refresh address valid from -REFRESH active.
Note: Refresh address refers to MODA0, A0-9 and MA0-9
----
45*
t263
-XMEMR active from OSC2 rise
----
55
t264
-XMEMR inactive from OSC2 rise
----
50
t265
-RAS0, -RAS3 active from -XMEMR fall
----
30
t266
-RAS0, -RAS3 inactive from -XMEMR rise
----
25
t267
-RAS1, -RAS2 active from -XMEMR fall
----
70
t268
-RAS1, -RAS2 inactive from -XMEMR rise
----
70
t269
LOMEGCS delay from -REFRESH
----
40
t270
-CAS fall from HLDA rise in CAS-RAS HLDA refesh
**
----
t271
-REFRESH active from PROCCLK in Hidden Refresh, or in HLDA
refresh in Early READY mode following memory write
----
50
t272
-XMEMR fall from PROCCLK in Hidden Refresh
----
50
t273
-XMEMR rise from PROCCLK in Hidden Refresh
----
50
*
** Not applicable to 82C836B. 10ns minimum for 82C836A.
40ns maximum for 82C836A.
Table 12-41.
Refresh----Formula Specifications
Symbol
Critical Path
Formula
Min.
Max.
te260
REF to XMEMR delay in HLDA refresh
t260-t263
----
16
te261
REF float after XMEMR rise
t261-t264
----
49
te270
CAS precharge in CAS-RAS refresh
t270-t103
*
----
te271
REF to XMEMR in early READY mode
t271-t263
----
16
te271a
REF to XMEMR delay in hidden refresh
t271-t272
----
5**
te272
XMEMR low time in hidden refresh
t272-t273
----
15***
te273
Address hold after XMEMR rise
t273-t271
----
23
*
** 1ns maximum for 82C836A.
*** 4ns maximum for 836A.
Not applicable for 82C836B. 9ns minimum for 82C836A.
I
AC Characteristics 25MHz
System Characteristics
12-20
Revision 3.0
P R E L I M I N A R Y
Chips and Technologies, Inc.