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參數(shù)資料
| 型號： | 935268625518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 11/82頁 |
| 文件大?。?/td> | 1965K |
| 代理商： | 935268625518 |
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Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
19 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
DDBGMODOUT[1:0]: interrupts for the DATA OUT endpoints 1 to 7.
The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow
the user to individually congure when the ISP1581 will send an interrupt to the
external microprocessor. Table 11 lists the available combinations.
Bit INTPOL controls the signal polarity of the INT output (active HIGH or LOW, rising
or falling edge). For level-triggering bit INTLVL must be made logic 0. By setting
INTLVL to logic 1 an interrupt will generate a pulse of 60 ns (edge-triggering).
[1]
First NAK: the rst NAK on an IN or OUT token after a previous ACK response.
9.2.4
Interrupt Enable register (address: 14H)
This register enables/disables individual interrupt sources. The interrupt for each
endpoint can be individually controlled via the associated IEPnRX or IEPnTX bits (‘n’
representing the endpoint number). All interrupts can be globally disabled via bit
GLINTENA in the Mode Register (see Table 7).
An interrupt is generated when the USB SIE receives or generates an ACK or NAK
on the USB bus. The interrupt generation depends on the Debug mode settings of bit
elds CDBGMOD, DDBGMODIN and DDBGMODOUT.
Table 9:
Interrupt Conguration register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
CDBGMOD[1:0]
DDBGMODIN[1:0]
DDBGMODOUT[1:0]
INTLVL
INTPOL
Reset
03H
0
Bus reset
03H
unchanged
Access
R/W
Table 10:
Interrupt Conguration register: bit description
Bit
Symbol
Description
7 to 6
CDBGMOD[1:0]
Control 0 Debug Mode: values see Table 11
5 to 4
DDBGMODIN[1:0]
Data Debug Mode IN: values see Table 11
3 to 2
DDBGMODOUT[1:0]
Data Debug Mode OUT: values see Table 11
1
INTLVL
Interrupt Level: selects the signaling mode on output
INT (0 = level, 1 = pulsed). In pulsed mode an interrupt
produces a 60 ns pulse. Bus reset value: unchanged.
0
INTPOL
Interrupt Polarity: selects signal polarity on output INT
(0 = active LOW, 1 = active HIGH). Bus reset value:
unchanged.
Table 11:
Debug mode settings
Value
CDBGMOD
DDBGMODIN
DDBGMODOUT
00H
Interrupt on all ACK and
NAK
Interrupt on all ACK
and NAK
Interrupt on all ACK, NYET
and NAK
01H
Interrupt on all ACK.
Interrupt on ACK
Interrupt on ACK and NYET
1XH
Interrupt on all ACK and
rst NAK[1]
Interrupt on all ACK
and rst NAK[1]
Interrupt on all ACK, NYET
and rst NAK[1]
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