參數(shù)資料
型號(hào)： 935268625518
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù)： 57/82頁
文件大?。?/td> 1965K
代理商： 935268625518
Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
60 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
14.3 DMA timing
14.3.1
PIO mode
(1) The device address consists of signals CS1, CS0, DA2, DA1 and DA0.
(2) The data bus width depends on the PIO access command used. Task File register access uses 8 bits (DATA[7:0]), except
for Task File register 1F0 which uses 16 bits (DATA[15:0]). DMA commands 04H and 05H also use a 16-bit data bus.
(3) The device can negate IORDY to extend the PIO cycle with wait states. The host determines whether or not to extend the
current cycle after tsu4 following the assertion of DIOR or DIOW. The following three cases are distinguished:
a). Device keeps IORDY released (high-impedance): no wait state is generated.
b). Device negates IORDY during tsu4, but re-asserts IORDY before tsu4 expires: no wait state is generated.
c). Device negates IORDY during tsu4 and keeps IORDY negated for at least 5 ns after tsu4 expires: a wait state is
generated. The cycle is completed as soon as IORDY is re-asserted. For extended read cycles (DIOR asserted), the read
data on lines DATAn must be valid at td1 before IORDY is asserted.
(4) DIOR and DIOW have a programmable polarity: shown here as active LOW signals.
Fig 18. PIO mode timing.
HIGH
(write) DATA[7:0](2)
(read) DATA[7:0](2)
device (1)
address
valid
DIOR, DIOW(4)
IORDY(3a)
IORDY(3b)
IORDY(3c)
tw1
tw2
th1
tsu1
tsu2
tsu5
tsu4
tw3
th2
tsu3
td2
th3(min)
Tcy1
MGT499
Table 78:
PIO mode timing parameters
VCC = 4.0 to 5.5 V; VGND =0V; Tamb = 40 to +85 °C.
Symbol
Parameter
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Unit
Tcy1(min)
read/write cycle time (minimum)
[1] 600
383
240
180
120
ns
tsu1(min)
address to DIOR/DIOW on set-up time
(minimum)
70
50
30
25
ns
tw1(min)
DIOR/DIOW pulse width (minimum)
[1] 165
125
100
80
70
ns
tw2(min)
DIOR/DIOW recovery time (minimum)
[1] ---70
25
ns
tsu2(min)
data set-up time before DIOW off
(minimum)
60
45
30
20
ns
th2(min)
data hold time after DIOW off (minimum)
30
20
15
10
ns
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