參數(shù)資料
型號(hào)： 935268625518
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁(yè)數(shù)： 35/82頁(yè)
文件大?。?/td> 1965K
代理商： 935268625518
Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
40 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
[1]
The short packet does not include zero-length packets.
9.4.8
DMA Interrupt Enable register (address: 54H)
This 2-byte register controls the interrupt generation of the source bits in the DMA
Interrupt Reason register (see Table 51). The bit allocation is given in Table 54. The
bit descriptions are given in Table 52. A logic 1 enables interrupt generation. The
values after a (bus) reset are logic 0 (disabled).
9
INTRQ_PENDING
A logic 1 indicates that a pending interrupt was detected on
pin INTRQ.
8
DMA_XFER_OK
A logic 1 indicates that the DMA transfer has been completed
(DMA Transfer Counter has become zero). This bit is only
used in GDMA (slave) mode and MDMA (master) mode.
7
1F0_WF_E
A logic 1 indicates that the 1F0 write FIFO is empty and the
microcontroller can start writing data.
6
1F0_WF_F
A logic 1 indicates that the 1F0 write FIFO is full and the
microcontroller must stop writing data.
5
1F0_RF_E
A logic 1 indicates that 1F0 read FIFO is empty and the
microcontroller must stop reading data.
4
READ_1F0
A logic 1 indicates that 1F0 FIFO contains unread data and
the microcontroller can start reading data.
3
BSY_DONE
A logic 1 indicates that the BSY status bit has become zero
and polling has been stopped.
2
TF_RD_DONE
A logic 1 indicates that the Read Task Files command has
been completed.
1
CMD_INTRQ_OK
A logic 1 indicates that all bytes from the FIFO have been
transferred (DMA Transfer Count zero) and an interrupt on pin
INTRQ was detected.
0
-
reserved
Table 53:
Internal EOT-Functional relation with DMA_XFER_OK bit
INT_EOT
DMA_XFER_OK Description
1
0
During the DMA transfer, there is a premature termination
with short packet[1].
1
DMA transfer is completed with short packet and the DMA
transfer counter has reached ‘0’.
0
1
DMA transfer is completed without any short packet and the
DMA transfer counter has reached ‘0’.
Table 52:
DMA Interrupt Reason Register: bit description…continued
Bit
Symbol
Description
Table 54:
DMA Interrupt Enable register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
IE_ODD
_IND
IE_EXT_EOT
IE_INT_EOT
IE_INTRQ_
PENDING
IE_DMA_
XFER_OK
Reset
-
0
0000
Bus reset
-
0
0000
Access
R/W
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