參數(shù)資料
型號： 935268625518
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù)： 21/82頁
文件大?。?/td> 1965K
代理商： 935268625518
Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
28 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
UDMA read/write (opcode = 02H/03H) — Ultra DMA mode for IDE transfers; the
specication of this mode can be obtained from the
ATA Specication Rev. 4. Pins
DA0 to DA2, CS0 and CS1 are used to select a device register for access. Control
signals are mapped as follows: DREQ (= DMARQ), DACK (= DMACK), DIOW
(= STOP), DIOR (= HDMARDY or HSTROBE), IORDY (= DSTROBE or DDMARDY).
Table 26:
Control bits for Generic DMA transfers
Control bits
Description
GDMA read/write (opcode = 00H/01H)
DMA Conguration register (see Table 33 and Table 34)
BURST[2:0]
determines the number of DMA cycles, during which pin
DREQ is kept asserted
MODE[1:0]
determines the active read/write data strobe signals
WIDTH0
selects the DMA bus width: 8 or 16 bits
DIS_XFER_CNT
disables the use of the DMA Transfer Counter
ATA_MODE
set to logic 0 (non-ATA transfer)
DMA Hardware register (see Table 35 and Table 36)
EOT_POL
selects the polarity of the EOT signal
ENDIAN[1:0]
determines whether the data is to be byte swapped or
normal. Applicable only in 16 bit mode.
ACK_POL, DREQ_POL,
WRITE_POL, READ_POL
select the polarity of the DMA handshake signals
MASTER
set to logic 0 (slave)
MDMA (Master) read/write (opcode = 06H/07H)
DMA Conguration register (see Table 33 and Table 34)
DMA_MODE[1:0]
determines the MDMA timings for the DIOR and DIOW
strobes (value 03H is used for UDMA only)
MODE[1:0]
determines the active data strobe(s).
WIDTH
selects the DMA bus width: 8 or 16 bits
DIS_XFER_CNT
disables the use of the DMA Transfer Counter
ATA_MODE
set to logic 1 (ATA transfer)
DMA Hardware register (see Table 35 and Table 36)
EOT_POL
input EOT is not used
ENDIAN[1:0]
determines whether the data is to be byte swapped or
normal. Applicable only in 16 bit mode.
ACK_POL, DREQ_POL,
WRITE_POL, READ_POL
select the polarity of the DMA handshake signals
MASTER
set to logic 1 (master)
Table 27:
Control bits for IDE-specied DMA transfers
Control bits
Description
PIO read/write (opcode = 04H/05H)
DMA Conguration register (see Table 33 and Table 34)
PIO_MODE[2:0]
selects the PIO mode; timings are ATA(PI) compatible
ATA_MODE
set to logic 1 (ATA transfer)
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