參數(shù)資料
型號(hào)： 935268625518
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁(yè)數(shù)： 3/82頁(yè)
文件大小： 1965K
代理商： 935268625518
Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
11 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.
Functional description
The ISP1581 is a high-speed USB device controller. It implements the Hi-Speed USB
and Original USB physical layer, the packet protocol layer and maintains up to 16
USB endpoints concurrently (control IN and control OUT, 7 IN and 7 OUT
congurable) along with Endpoint EP0SETUP, which is used to access the setup
buffer.
USB Chapter 9 protocol handling is executed by means of external rmware.
The ISP1581 has a fast general-purpose interface for communication with most types
of microcontrollers/processors. This Microcontroller Interface is congured by pins
BUS_CONF, MODE1 and MODE0 to accommodate most interface types. Two bus
congurations are available, selected via input BUS_CONF during power-up:
Generic Processor mode (BUS_CONF = 1):
– AD[7:0]: 8-bit address bus (selects target register)
– DATA[15:0]: 16-bit data bus (shared by processor and DMA)
– Control signals: R/W and DS or RD and WR (selected via pin MODE0), CS
– DMA interface (generic slave mode only): uses lines DATA[15:0] as data bus,
DIOR and DIOW as dedicated read and write strobes.
Split Bus mode (BUS_CONF = 0):
– AD[7:0]: 8-bit local microprocessor bus (multiplexed address/data)
– DATA[15:0]: 16-bit DMA data bus
– Control signals: CS, ALE or A0 (selected via pin MODE1), R/W and DS or RD
and WR (selected via pin MODE0)
– DMA interface (master or slave mode): uses DIOR and DIOW as dedicated read
and write strobes.
For high-bandwidth data transfer, the integrated DMA handler can be invoked to
transfer data to/from external memory or devices. The DMA Interface can be
congured by writing to the proper DMA registers (see Section 9.4).
The ISP1581 supports Hi-Speed USB and Original USB signaling. Detection of the
USB signaling speed is done automatically.
ISP1581 has 8 kbytes of internal FIFO memory, which is shared among the enabled
USB endpoints.
There are 7 IN endpoints, 7 OUT endpoints and 2 control endpoints that are a xed
64 bytes long. Any of the 7 IN and 7 OUT endpoints can be separately enabled or
disabled. The endpoint type (interrupt, isochronous or bulk) and packet size of these
endpoints can be individually congured depending on the requirements of the
application. Optional double buffering increases the data throughput of these data
endpoints.
The ISP1581 requires a single supply of 3.3 V or 5.0 V, depending on the I/O voltage.
It has 5.0 V tolerant I/O pads and has an internal 3.3 V regulator for powering the
analog transceiver.
The ISP1581 operates on a 12 MHz crystal oscillator. An integrated 40
× PLL clock
multiplier generates the internal sampling clock of 480 MHz.
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