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參數(shù)資料
| 型號： | 935268625518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 13/82頁 |
| 文件大?。?/td> | 1965K |
| 代理商： | 935268625518 |
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Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
20 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
All data IN transactions use the Transmit buffers (TX), which are handled by the
DDBGMODIN bits. All data OUT transactions go via the Receive buffers (RX), which
are handled by the DDBGMODOUT bits. Transactions on Control endpoint 0 (IN,
OUT and SETUP) are handled by the CDBGMOD bits.
Interrupts caused by events on the USB bus (SOF, Pseudo SOF, suspend, resume,
bus reset, Setup and High-Speed Status) can also be controlled individually. A bus
reset disables all enabled interrupts except bit IEBRST (bus reset), which remains
unchanged.
The Interrupt Enable Register consists of 4 bytes. The bit allocation is given in
Table 12:
Interrupt Enable register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
IEP7TX
IEP7RX
Reset
-
----
0
Bus Reset
-
----
0
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
IEP6TX
IEP6RX
IEP5TX
IEP5RX
IEP4TX
IEP4RX
IEP3TX
IEP3RX
Reset
0
0000
00
Bus Reset
0
0000
00
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
IEP2TX
IEP2RX
IEP1TX
IEP1RX
IEP0TX
IEP0RX
reserved
IEP0SETUP
Reset
0
0000
-
0
Bus Reset
0
0000
-
0
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
IEDMA
IEHS_STA
IERESM
IESUSP
IEPSOF
IESOF
IEBRST
Reset
-
0
0000
00
Bus Reset
-
0
0000
0
unchanged
Access
R/W
Table 13:
Interrupt Enable register: bit description
Bit
Symbol
Description
31 to 26
-
reserved; must write logic 0
25 to 12
IEP7TX to
IEP1RX
A logic 1 enables interrupt from the indicated endpoint.
11
IEP0TX
A logic 1 enables interrupt from the Control IN endpoint 0.
10
IEP0RX
A logic 1 enables interrupt from the Control OUT endpoint 0.
9
-
reserved
8
IEP0SETUP
A logic 1 enables the interrupt for the Setup data received on
endpoint 0.
7
-
reserved
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