參數(shù)資料
型號: 935268625518
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 18/82頁
文件大?。?/td> 1965K
代理商: 935268625518
Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
25 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9.3.5
Endpoint MaxPacketSize register (address: 04H)
This register determines the maximum packet size for all endpoints except Control 0.
The register contains 2 bytes and the bit allocation is given in Table 22.
Each time the register is written, the Buffer Length registers of all endpoints are
re-initialized to the FFOSZ eld value. The NTRANS bits control the number of
transactions allowed in a single micro-frame (for high-speed Isochronous and
interrupt endpoints only).
Table 21:
Buffer Length register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
DATACOUNT[15:8]
Reset
00H
Bus reset
00H
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
DATACOUNT[7:0]
Reset
00H
Bus reset
00H
Access
R/W
Table 22:
Endpoint MaxPacketSize register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
NTRANS[1:0]
FFOSZ[10:8]
Reset
-
00H
Bus reset
-
00H
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
FFOSZ[7:0]
Reset
00H
Bus reset
00H
Access
R/W
Table 23:
Endpoint MaxPacketSize register: bit description
Bit
Symbol
Description
15 to 13
reserved
12 to 11
NTRANS[1:0]
Number of Transactions (HS mode only):
0 — 1 packet per microframe
1 — 2 packets per microframe
2 — 3 packets per microframe
3 — reserved.
These bits are applicable for Isochronous/interrupt transactions
only.
10 to 0
FFOSZ[10:0]
FIFO Size: Sets the FIFO size in bytes for the indexed endpoint.
Applies to both HS and FS operation.
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