參數(shù)資料
型號: ADSP-21371KSWZ-2B
廠商: Analog Devices Inc
文件頁數(shù): 27/48頁
文件大小: 0K
描述: IC DSP 32BIT 266MHZ 208-LQFP
產(chǎn)品培訓(xùn)模塊: SHARC Processor Overview
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點
接口: DAI,DPI
時鐘速率: 266MHz
非易失內(nèi)存: ROM(512 kB)
芯片上RAM: 128kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 208-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 208-LQFP-EP(28x28)
包裝: 托盤
ADSP-21371
Input Data Port (IDP)
The timing requirements for the IDP are given in Table 31. IDP
signals (SCLK, FS, and SDATA) are routed to the DAI_P20–1
pins using the SRU. Therefore, the timing specifications pro
vided below are valid at the DAI_P20–1 pins.
Table 31. Input Data Port (IDP)
Parameter
Min
Max
Unit
Timing Requirements
tSISFS
1
FS Setup Before SCLK Rising Edge
3.8
ns
tSIHFS
1
FS Hold After SCLK Rising Edge
2.5
ns
tSISD
1
SData Setup Before SCLK Rising Edge
2.5
ns
tSIHD
1
SData Hold After SCLK Rising Edge
2.5
ns
tIDPCLKW
Clock Width
9
ns
tIDPCLK
Clock Period
24
ns
1 DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
SAMPLE EDGE
DAI_P20
-1
(SCLK)
DAI_P20
-1
(FS)
tSISFS
tSIHFS
tIPDCLK
DAI_P20
-1
(SDATA)
tIPDCLKW
tSISD
tSIHD
Figure 21. IDP Master Timing
Rev. 0
|
Page 33 of 48
|
June 2007
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