參數(shù)資料
型號(hào)： ADSP-21371KSWZ-2B
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 39/48頁(yè)
文件大小： 0K
描述： IC DSP 32BIT 266MHZ 208-LQFP
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： DAI，DPI
時(shí)鐘速率： 266MHz
非易失內(nèi)存： ROM（512 kB）
芯片上RAM： 128kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 208-LQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 208-LQFP-EP（28x28）
包裝： 托盤(pán)
)
10
The ac signal specifications (timing parameters) appear in
output disable time, output enable time, and capacitive loading.
The timing specifications for the SHARC apply for the voltage
reference levels in Figure 35.
Figure 34 shows typical I-V characteristics for the output driv
ers of the ADSP-21371. The curves represent the current drive
capability of the output drivers as a function of output voltage.
S
O
U
R
C
E
(
V
)
N
T
m
A
D
E
X
T
ADSP-21371
OUTPUT DRIVE CURRENTS
40
30
20
3.47V, -45°C
3.3V, 25°C
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 35). Figure 39 shows graphically
how output delays and holds vary with load capacitance. The
graphs of Figure 37, Figure 38, and Figure 39 may not be linear
outside the ranges shown for Typical Output Delay vs. Load
Capacitance and Typical Output Rise Time (20% to 80%,
V = Min) vs. Load Capacitance.
12
R
S
E
A
N
F
T
M
(
n
s
)
I
D
L
R
I
S
E
A
N
D
F
L
T
M
n
s
VOH
3.3V, 25°C
3.11V, 125°C
VOL
3.47V, 45°C
y = 0.0467x + 1.6323
RIS
FALL
E
y = 0.045x + 1.524
10
0
-
10
8
-
20
6
-
30
4
-
40
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SWEEP (VDDEXT) VOLTAGE (V)
2
Figure 34. ADSP-21371 Typical Drive at Junction Temperature
TEST CONDITIONS
Timing is measured on signals when they cross the 1.5 V level as
described in Figure 36. All delays (in nanoseconds) are mea
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 37. Typical Output Rise/Fall Time (20% to 80%,
VDDEXT = Max)
12
RISE
y = 0.049x + 1.5105
FALL
y = 0.0482x + 1.4604
10
8
50
6
TO
OUTPUT
1.5V
PIN
4
30pF
2
0
50
100
150
200
250
Figure 35. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
LOAD CAPACITANCE (pF)
Figure 38. Typical Output Rise/Fall Time (20% to 80%,
VDDEXT = Min)
June 2007
INPUT
OR
1.5V
1.5V
OUTPUT
Figure 36. Voltage Reference Levels for AC Measurements
Rev. 0
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