參數(shù)資料
型號(hào): ADSP-21371KSWZ-2B
廠商: Analog Devices Inc
文件頁(yè)數(shù): 32/48頁(yè)
文件大?。?/td> 0K
描述: IC DSP 32BIT 266MHZ 208-LQFP
產(chǎn)品培訓(xùn)模塊: SHARC Processor Overview
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點(diǎn)
接口: DAI,DPI
時(shí)鐘速率: 266MHz
非易失內(nèi)存: ROM(512 kB)
芯片上RAM: 128kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 208-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 208-LQFP-EP(28x28)
包裝: 托盤
ADSP-21371
S/PDIF Receiver
The following section describes timing as it relates to the
S/PDIF receiver.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × FS clock.
Table 36. S/PDIF Receiver Internal Digital PLL Mode Timing
Parameter
Min
Max
Unit
Switching Characteristics
tDFSI
LRCLK Delay After SCLK
tHOFSI
LRCLK Hold After SCLK
tDDTI
Transmit Data Delay After SCLK
tHDTI
Transmit Data Hold After SCLK
tSCLKIW
1
Transmit SCLK Width
–2
38.5
5
ns
1 SCLK frequency is 64 × FS where FS = the frequency of LRCLK.
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(DATA CHANNEL A/B)
DRIVE EDGE
SAMPLE EDGE
tSCLKIW
tDFSI
tDDTI
tHOFSI
tHDTI
Figure 28. S/PDIF Receiver Internal Digital PLL Mode Timing
Rev. 0
|
Page 38 of 48
|
June 2007
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