參數(shù)資料
型號： ADSP-21371KSWZ-2B
廠商： Analog Devices Inc
文件頁數(shù)： 4/48頁
文件大?。?/td> 0K
描述： IC DSP 32BIT 266MHZ 208-LQFP
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： DAI，DPI
時鐘速率： 266MHz
非易失內(nèi)存： ROM（512 kB）
芯片上RAM： 128kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 208-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 208-LQFP-EP（28x28）
包裝： 托盤
ADSP-21371
PIN FUNCTION DESCRIPTIONS
The following symbols appear in the Type column of Table 5:
A = asynchronous, I = input, O = output, S = synchronous,
(A/D) = active drive, (O/D) = open drain, and T = three-state,
(pd) = pull-down resistor, (pu) = pull-up resistor.
Table 5. Pin List
Name
Type
State During
and After Reset Description
ADDR23–0
O/T (pu)
Pulled high/
driven low
External Address. The ADSP-21371 outputs addresses for external memory and periph
erals on these pins.
DATA31–0
I/O (pu)
Pulled high/
pulled high
External Data. The data pins can be multiplexed to support the external memory interface
data (I/O), the PDAP (I), FLAGS (I/O) and PWM (O). After reset, all DATA pins are in EMIF
mode and FLAG(0-3) pins will be in FLAGS mode (default). When configured in the
IDP_PDAP_CTL register, IDP channel 0 scans the DATA31–8 pins for parallel input
data.
DAI _P20–1
I/O with
programmable pu1
Pulled high/
pulled high
Digital Applications Interface Pins. These pins provide the physical interface to the DAI
SRU. The DAI SRU configuration registers define the combination of on-chip audiocentric
peripheral inputs or outputs connected to the pin and to the pin’s output enable. The
configuration registers of these peripherals then determines the exact behavior of the pin.
Any input or output signal present in the DAI SRU may be routed to any of these pins. The
DAI SRU provides the connection from the serial ports, the S/PDIF module, input data ports
(2), and the precision clock generators (4), to the DAI_P20–1 pins. Pullups can be disabled
via the DAI_PIN_PULLUP register.
DPI _P14–1
I/O with
programmable pu1
Pulled high/
pulled high
Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.
The DPI SRU configuration registers define the combination of on-chip peripheral inputs
or outputs connected to the pin and to the pin’s output enable. The configuration registers
of these peripherals then determines the exact behavior of the pin. Any input or output
signal present in the DPI SRU may be routed to any of these pins. The DPI SRU provides the
connection from the timers (2), SPIs (2), UART (1), flags (12), and general-purpose I/O (9) to
the DPI_P14–1 pins. Pull-ups can be disabled via the DPI_PIN_PULLUP register.
ACK
I (pu)
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an
external memory access. ACK is used by I/O devices, memory controllers, or other periph
erals to hold off completion of an external memory access.
RD
O/T (pu)
Pulled high/
driven high
External Port Read Enable. RD is asserted whenever the ADSP-21371 reads a word from
external memory. RD has a 22.5 k
Ω internal pull-up resistor.
WR
O/T (pu)
Pulled high/
driven high
External Port Write Enable. WR is asserted when the ADSP-21371 writes a word to
external memory. WR has a 22.5 k
Ω internal pull-up resistor.
SDRAS
O/T (pu)
Pulled high/
driven high
SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other
SDRAM command pins, defines the operation for the SDRAM to perform.
SDCAS
O/T (pu)
Pulled high/
driven high
SDRAM Column Address Select. Connect to SDRAM's CAS pin. In conjunction with other
SDRAM command pins, defines the operation for the SDRAM to perform.
SDWE
O/T (pu)
Pulled high/
driven high
SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.
SDCKE
O/T (pu)
Pulled high/
driven high
SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK signal.
For details, see the data sheet supplied with the SDRAM device.
SDA10
O/T (pu)
Pulled high/
driven low
SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a non-
SDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.
SDCLK
O/T
High-Z/driving
SDRAM Clock.
MS0–1
O/T (pu)
Pulled high/
driven high
Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre
sponding banks of external memory. The MS3-0 lines are decoded memory address lines
that change at the same time as the other address lines. When no external memory access
is occurring the MS3-0 lines are inactive; they are active however when a conditional
memory access instruction is executed, whether or not the condition is true.
The MS1 pin can be used in EPORT/FLASH boot mode. For more information, see the
ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21367/8/9 Processors.
Rev. 0
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Page 12 of 48
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June 2007
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