ADSP-21371
SPI Interface—Slave
Table 38. SPI Interface Protocol—Slave Switching and Timing Specifications
Parameter
Min
Max
Unit
Timing Requirements
tSPICLKS
Serial Clock Cycle
tSPICHS
Serial Clock High Period
tSPICLS
Serial Clock Low Period
tSDSCO
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
tHDS
Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0
tSSPIDS
Data Input Valid to SPICLK edge (Data Input Set-up Time)
tHSPIDS
SPICLK Last Sampling Edge to Data Input Not Valid
tSDPPW
SPIDS Deassertion Pulse Width (CPHASE=0)
Switching Characteristics
tDSOE
SPIDS Assertion to Data Out Active
tDSDHI
SPIDS Deassertion to Data High Impedance
tDDSPIDS
SPICLK Edge to Data Out Valid (Data Out Delay Time)
tHDSPIDS
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
tDSOV
SPIDS Assertion to Data Out Valid (CPHAS E = 0)
4 × tPCLK – 2
2 × tPCLK – 2
2 × tPCLK
2
2 × tPCLK
0
2 × tPCLK
6.8
9.5
5 × tPCLK
ns
SPIDS
(INPUT)
SPICLK
(CP = 0)
(INPUT)
SPICLK
(CP = 1)
(INPUT)
MISO
MOSI
(INPUT)
(OUTPUT)
CPHASE = 1
MISO
(OUTPUT)
MOSI
(INPUT)
CPHASE = 0
tHSPIDS
tDDSPIDS
tDSDHI
LSB
MSB
MSB VALID
tDSOE
tDDSPIDS
tHDSPIDS
tSSPIDS
tSDSCO
tSPIC HS
tSPICLS
tSPICLKS
tHDS
tSPICHS
tSSPIDS
tHSPIDS
tDSDHI
LSB VALID
MSB
MSB VALID
tDDSPIDS
tSSPIDS
LSB VALID
LSB
tSDPPW
tDSOV
tHDSPIDS
Figure 30. SPI Slave Timing
Rev. 0
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Page 40 of 48
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June 2007