參數(shù)資料
型號: ADSP-21371KSWZ-2B
廠商: Analog Devices Inc
文件頁數(shù): 33/48頁
文件大?。?/td> 0K
描述: IC DSP 32BIT 266MHZ 208-LQFP
產(chǎn)品培訓(xùn)模塊: SHARC Processor Overview
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點(diǎn)
接口: DAI,DPI
時(shí)鐘速率: 266MHz
非易失內(nèi)存: ROM(512 kB)
芯片上RAM: 128kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 208-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 208-LQFP-EP(28x28)
包裝: 托盤
ADSP-21371
SPI Interface—Master
The ADSP-21371 contains two SPI ports. Both primary and sec
ondary are available through DPI only. The timing provided in
Table 37 and Table 38 applies to both.
Table 37. SPI Interface ProtocolMaster Switching and Timing Specifications
Parameter
Min
Max
Unit
Timing Requirements
tSSPIDM
Data Input Valid To SPICLK Edge (Data Input Setup Time)
8.2
ns
tHSPIDM
SPICLK Last Sampling Edge To Data Input Not Valid
2
ns
Switching Characteristics
tSPICLKM
Serial Clock Cycle
8 × tPCLK – 2
ns
tSPICHM
Serial Clock High Period
4 × tPCLK – 2
ns
tSPICLM
Serial Clock Low Period
4 × tPCLK – 2
ns
tDDSPIDM
SPICLK Edge to Data Out Valid (Data Out Delay Time)
2.5
tHDSPIDM
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
2
ns
tSDSCIM
FLAG3–0IN (SPI device select) Low to First SPICLK Edge
4 × tPCLK – 2
ns
tHDSM
Last SPICLK Edge to FLAG3–0IN High
4 × tPCLK – 2
ns
tSPITDM
Sequential Transfer Delay
4 × tPCLK – 1
ns
FLAG3
-0
(OUTPUT)
SPICLK
(CP = 0)
(OUTPUT)
SPICLK
(CP = 1)
(OUTPUT)
CPHASE = 1
MOSI
(OUTPUT)
MISO
(INPUT)
CPHASE = 0
MOSI
(OUTPUT)
MISO
(INPUT)
LSB
VALID
MSB
VALID
tSSPIDM
tHSPIDM
tHDSPIDM
LSB
MSB
tHSPIDM
tDDSPIDM
tSPICHM
tSPICLM
tSPICLKM
tSPICHM
tHDSM
tSPITDM
tHDSPIDM
LSB
VALID
LSB
MSB
VALID
tHSPIDM
tDDSPIDM
tSSPIDM
tSDSCIM
tSSPIDM
Figure 29. SPI Master Timing
Rev. 0
|
Page 39 of 48
|
June 2007
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