參數(shù)資料
型號: ADSP-21371KSWZ-2B
廠商: Analog Devices Inc
文件頁數(shù): 6/48頁
文件大?。?/td> 0K
描述: IC DSP 32BIT 266MHZ 208-LQFP
產(chǎn)品培訓(xùn)模塊: SHARC Processor Overview
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點
接口: DAI,DPI
時鐘速率: 266MHz
非易失內(nèi)存: ROM(512 kB)
芯片上RAM: 128kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 208-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 208-LQFP-EP(28x28)
包裝: 托盤
ADSP-21371
DATA MODES
The upper 32 data pins of the external memory interface are
muxed (using bits in the SYSCTL register) to support the exter
nal memory interface data (input/output), the PDAP (input
only), and the FLAGS (input/output). Table 6 provides the pin
settings.
Table 6. Function of Data Pins
DATA PIN MODE
DATA31–16
DATA15–8
DATA7–0
000
EPDATA32–0
001
FLAGS/PWM15–01
EPDATA15–0
010
FLAGS/PWM15–01
FLAGS15–8
EPDATA7–0
011
FLAGS/PWM15–01
FLAGS15–0
100
PDAP (DATA + CTRL)
EPDATA7–0
101
PDAP (DATA + CTRL)
FLAGS7–0
110
Reserved
111
Three-state all pins
1 These signals can be FLAGS or PWM or a mix of both. However, they can be selected only in groups of four. Their function is determined by the control signals
FLAGS/PWM_SEL. For more information, see the ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21367/8/9 Processors.
BOOT MODES
Table 7. Boot Mode Selection
BOOTCFG1–0
Booting Mode
00
SPI Slave Boot
01
SPI Master Boot
10
EPROM/FLASH Boot
CORE INSTRUCTION RATE TO CLKIN RATIO MODES
For details on processor timing, see Timing Specifications and
Table 8. Core Instruction Rate/ CLKIN Ratio Selection
CLKCFG1–0
Core to CLKIN Ratio
00
6:1
01
32:1
10
16:1
Rev. 0
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Page 14 of 48
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June 2007
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