參數(shù)資料
型號(hào)： AM5X86
廠商： Advanced Micro Devices, Inc.
英文描述： High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能單片32位微處理器)
中文描述： 高性能設(shè)計(jì)的片上集成完整的32位架構(gòu)Micrprocessor（高性能單片32位微處理器）
文件頁(yè)數(shù)： 18/67頁(yè)
文件大?。?/td> 1201K
代理商： AM5X86
18
Am5
X
86 Microprocessor
AMD
PRELIMINARY
4.3.3
Protected mode provides access to the sophisticated
memory management paging and privilege capabilities
of the processor.
Protected Mode
4.3.4
SMM is a special operating mode described in detail in
Section 7.
System Management Mode
4.4
The Am5
X
86 microprocessor family supports a superset
architecture of the standard 486 cache implementation.
This architectural enhancement improves not only CPU
performance, but total system performance.
Cache Architecture
4.4.1
The standard 486DX-type write-through cache architec-
ture is characterized by the following:
Write-Through Cache
I
External read accesses are placed in the cache if
they meet proper caching requirements.
I
Subsequent reads to the data in the cache are made
if the address is stored in the cache tag array.
I
Write operations to a valid address in the cache are
updated in the cache andto external memory. This
data writing technique is called write-through
The write-through cache implementation forces all
writes to flow through to the external bus and back to
main memory. Consequently, the write-through cache
generates a large amount of bus traffic on the external
data bus.
4.4.2
The microprocessor write-back cache architecture is
characterized by the following:
Write-Back Cache
I
External read accesses are placed in the cache if
they meet proper caching requirements.
I
Subsequent reads to the data in the cache are made
if the address is stored in the cache tag array.
I
Write operations to a valid address in the cache that
is in the write-through (shared) state is updated in
the cache and to external memory.
I
Write operations to a valid address in the cache that
is in the write-back (exclusive or modified) state is
updated onlyin the cache. External memory is not
updated at the time of the cache update.
I
Modified data is written back to external memory
when the modified cache line is being replaced with
a new cache line (copy-back operation) or an exter-
nal bus master has snooped a modified cache line
(write-back).
The write-back cache feature significantly reduces the
amount of bus traffic on the external bus; however, it
also adds complexity to the system design to maintain
memory coherency. The write-back cache requires en-
4
4.1
Am5
X
86 microprocessors use a 32-bit architecture with
on-chip memory management and cache memory units.
The instruction set includes the complete 486 micropro-
cessor instruction set along with extensions to serve the
new extended applications. All software written for the
486 microprocessor and previous members of the x86
architectural family can run on the Am5
X
86 micropro-
cessor without modification.
FUNCTIONAL DESCRIPTION
Overview
The on-chip Memory Management Unit (MMU) is com-
pletely compatible with the 486 MMU. The MMU in-
cludes a segmentation unit and a paging unit.
Segmentation allows management of the logical ad-
dress space by providing easy data and code relocati-
bility and efficient sharing of global resources. The
paging mechanism operates beneath segmentation and
is transparent to the segmentation process. Paging is
optional and can be disabled by system software. Each
segment can be divided into one or more 4-Kbyte seg-
ments. To implement a virtual memory system, the
Am5
X
86 microprocessor supports full restartability for
all page and segment faults.
4.2
Memory is organized into one or more variable length
segments, each up to 4 Gbytes (2
32
bytes). A segment
can have attributes associated with it, including its lo-
cation, size, type (i.e., stack, code, or data), and protec-
tion characteristics. Each task on a microprocessor can
have a maximum of 16,381 segments, each up to 4
Gbytes. Thus, each task has a maximum of 64 Tbytes
of virtual memory.
Memory
The segmentation unit provides four levels of protection
for isolating and protecting applications and the operat-
ing system from each other. The hardware-enforced
protection allows high-integrity system designs.
4.3
The Am5
X
86 microprocessor has four modes of opera-
tion: Real Address mode (Real mode), Virtual 8086 Ad-
dress mode (Virtual mode), Protected Address mode
(Protected mode), and System Management mode
(SMM).
Modes of Operation
4.3.1
In Real mode, the Am5
X
86 microprocessor operates as
a fast 8086. Real mode is required primarily to set up
the processor for Protected mode operation.
Real Mode
4.3.2
In Virtual mode, the processor appears to be in Real
mode, but can use the extended memory accessing of
Protected mode.
Virtual Mode
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