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參數(shù)資料
| 型號： | AM5X86 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能單片32位微處理器) |
| 中文描述： | 高性能設(shè)計的片上集成完整的32位架構(gòu)Micrprocessor（高性能單片32位微處理器） |
| 文件頁數(shù)： | 31/67頁 |
| 文件大小： | 1201K |
| 代理商： | AM5X86 |
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Am5
X
86 Microprocessor
31
AMD
PRELIMINARY
Step 10In the same clock cycle, the snooping cache
drives HITM back to 1.
Step 11The write of data A is finished if BRDY transi-
tions to 0 (BLAST = 0), because it is a single
word.
The software write sequence was first data A and then
data B. But on the external bus the data appear first as
data B and then data A. The order of writes is changed.
In most cases, it is unnecessary to strictly maintain the
ordering of writes. However, some cases (for example,
writing to hardware control registers) require writes to
be observed externally in the same order as pro-
grammed. There are two options to ensure serialization
of writes, both of which drive the cache to Write-through
mode:
1.
2.
Set the PWT bit in the page table entries.
Drive the WB/WT signal Low when accessing these
memory locations.
Option 1 is an operating-system-level solution not di-
rectly implemented by user-level code. Option 2, the
hardware solution, is implemented at the system level.
BLAST
Data
BRDY
EADS
ADS
HITM
Cached Data
AHOLD
CLK
Write Buffer
B original
1
A
2
6
5
B modified
4
3
B
B+4
B+8
B+12
8
A
Ignored
9
7
XXX
Note:
The circled numbers in this figure represent the steps in section 4.8.7.1.
Figure 14. Write Cycle Reordering Due to Buffering
10
11
Step 3 The next write of the processor hits the cache
and the line is non-shared. Therefore, data B is
written into the cache. The cache line transits
to the modified state.
Step 4 In the same clock cycle, a snoop request to the
same address where data B resides is started
because EADS = 0. The snoop hits a modified
line. EADS is ignored due to the hit of a modified
line, but is detected again as early as in step 10.
Step 5 Two clock cycles after EADS asserts, HITM be-
comes valid.
Step 6 Because the processor-initiated access cannot
be finished (AHOLD is still 1), the BIU gives
priority to a write-back access that does not re-
quire the use of the address bus. Therefore, in
the clock cycle, the cache starts the write-back
sequence indicated by ADS = 0 and W/R = 0.
Step 7 During the write-back sequence, AHOLD is
deasserted.
Step 8 The write-back access is finished when BLAST
and BRDY transition to 0.
Step 9 After the last write-back access, the BIU starts
writing data A from the write buffers. This is
indicated by ADS = 0 and W/R = 0.
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