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參數(shù)資料
| 型號(hào)： | AM5X86 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能單片32位微處理器) |
| 中文描述： | 高性能設(shè)計(jì)的片上集成完整的32位架構(gòu)Micrprocessor（高性能單片32位微處理器） |
| 文件頁數(shù)： | 33/67頁 |
| 文件大小： | 1201K |
| 代理商： | AM5X86 |
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Am5
X
86 Microprocessor
33
AMD
PRELIMINARY
4.9
Cache Invalidation and Flushing in
Write-Back Mode
The Am5
X
86 microprocessor family supports cache in-
validation and flushing, much like the Am486 micropro-
cessor Write-through mode. However, the addition of
the write-back cache adds some complexity.
4.9.1
To invalidate the on-chip cache, the Am5
X
86 micropro-
cessor family uses the same instructions as the Am486
microprocessor family. The two invalidation instruc-
tions, INVD and WBINVD, while similar, are slightly dif-
ferent for use in the write-back environment.
Cache Invalidation through Software
The WBINVD instruction first performs a write-back of
the modified data in the cache to external memory. Then
it invalidates the cache, followed by two special bus
cycles. The INVD instruction only invalidates the cache,
regardless of whether modified data exists, and follows
with a special bus cycle. The utmost care should be
taken when executing the INVD instruction to ensure
memory coherency. Otherwise, modified data may be
invalidated prior to writing back to main memory. In
Write-back mode, WBINVD requires a minimum of 4100
internal clocks to search the cache for modified data.
Writing back modified data adds to this minimum time.
WBINVD can only be stopped by a RESET.
Two special bus cycles follow the write-back of modified
data upon execution of the WBINVD instruction: first the
write-back, and then the flush special bus cycle. The
INVD operates identically to the standard 486 micropro-
cessor family in that the flush special bus cycle is gen-
erated when the on-chip cache is invalidated. Table 7
specifies the special bus cycle states for the instructions
WBINVD and INVD.
4.9.2
The other mechanism for cache invalidation is the
FLUSH pin. The FLUSH pin operates similarly to the
WBINVD command, writing back modified cache lines
to main memory. After the entire cache has copied back
all the modified data, the microprocessor generates two
special bus cycles. These special bus cycles signal to
the external caches that the microprocessor on-chip
cache has completed its copy-back and that the second
level cache may begin its copy-back to memory, if so
required.
Cache Invalidation through Hardware
Two flush acknowledge cycles are generated after the
FLUSH pin is asserted and the modified data in the
cache is written back. As with the WBINVD instruction,
in Write-back mode, a flush requires a minimum of 4100
internal clocks to test the cache for modified data. Writ-
ing back modified data adds to this minimum time. The
flush operation can only be stopped by a RESET. Table
8 shows the special flush bus cycle configuration.
Table 7. WBINVD/INVD Special Bus Cycles
A32–A2
0000 0000 h
M/IO D/C W/R BE3 BE2 BE1 BE0 Bus Cycle
0
0
1
0
1
0
0
1
1
1
1
0
1
1
Write-back
1
Flush
1, 2
0000 0000 h
Notes:
1. WBINVD generates first write-back, then flush.
2. INVD generates only flush.
BRDY
BLAST
ADS
HITM
EADS
AHOLD
ADR
CLK
n
S
Figure 15. Latest Snooping of Copy-Back
CACHE
Address B
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