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參數(shù)資料
| 型號： | AM5X86 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能單片32位微處理器) |
| 中文描述： | 高性能設(shè)計的片上集成完整的32位架構(gòu)Micrprocessor（高性能單片32位微處理器） |
| 文件頁數(shù)： | 26/67頁 |
| 文件大?。?/td> | 1201K |
| 代理商： | AM5X86 |
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26
Am5
X
86 Microprocessor
AMD
Step 3 Two clock cycles after EADS is asserted, HITM
becomes valid, and is 0 because the line is mod-
ified.
Step 4 In the next clock, the core system logic deas-
serts the HOLD signal in response to the
HITM = 0 signal. The core system logic backs
off the current bus master at the same time so
that the microprocessor can access the bus.
HOLD can be reasserted immediately after
ADS is asserted for burst cycles.
Step 5
The snooping cache starts it’s write-back of the
modified line by asserting ADS = 0, CACHE = 0,
and W/R = 1. The write access is a burst write.
The number of clock cycles between deassert-
ing HOLD to the snooping cache and first
asserting ADS for the write-back cycles can
vary. In this example, it is one clock cycle, which
is the shortest possible time. Regardless of the
number of clock cycles, the start of the write-
back is seen by ADS going Low.
Step 6 The write-back access is finished when BLAST
and BRDY both are 0.
Step 7 In the clock cycle after the final write-back ac-
cess, the processor drives HITM back to 1.
Step 8 HOLD is sampled by the microprocessor.
Step 9 One cycle after sampling HOLD High, the mi-
croprocessor transitions HLDA transitions to 1,
acknowledging the HOLD request.
Step 10The core system logic removes hold-off control
to the external bus master. This allows the ex-
ternal bus master to immediately retry the abort-
ed access. ADS is strobed Low, which
generates EADS Low in the same clock cycle.
Step 11The bus master restarts the aborted access.
EADS and INV are applied to the microproces-
sor as before. This starts another snoop cycle.
The status of the addressed line is now either shared
(INV = 0) or is changed to invalid (INV = 1).
4.8.5
Scenario
: The following occurs when, in addition to the
write-back operation, other bus accesses initiated by
the processor associated with the snooped cache are
pending. The microprocessor gives the write-back ac-
cess priority. This implies that if HOLD is deasserted,
the microprocessor first writes back the modified line
(see Figure 9).
Write-Back and Pending Access
Figure 9. Write-Back and Pending Access
Note:
The circled numbers in this figure represent the steps in section 4.8.5.
EADS
External
bus master’s
BOFF signal
HLDA
Data
HOLD
HITM
ADS
INV
BRDY
BLAST
W/R
M/IO
CACHE
ADR
CLK
valid
n
n
n
n+4
n+8 n+12
n+12
valid
n
2
3
1
7
8
9
10
6
5
11
floating/tri-stated
4
n+8
n+4
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