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參數(shù)資料
| 型號： | AM5X86 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能單片32位微處理器) |
| 中文描述： | 高性能設(shè)計的片上集成完整的32位架構(gòu)Micrprocessor（高性能單片32位微處理器） |
| 文件頁數(shù)： | 7/67頁 |
| 文件大小： | 1201K |
| 代理商： | AM5X86 |
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AMD
PRELIMINARY
Am5
X
86 Microprocessor
7
Figure 30 SMM Base Slot Offset .............................................................................................................48
Figure 31 SRAM Usage ..........................................................................................................................48
Figure 32 SMRAM Location ....................................................................................................................49
Figure 33 SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Through Mode
with Caching Enabled During SMM..........................................................................................50
Figure 34 SMM Timing in Systems Using Non-Overlaid Memory Spaces and Write-Back Mode with
Caching Enabled During SMM.................................................................................................50
Figure 35 SMM Timing in Systems Using Non-Overlaid Memory Spaces and Write-Back Mode with
Caching Disabled During SMM................................................................................................50
Figure 36 SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode with
Caching Enabled During SMM.................................................................................................51
Figure 37 SMM Timing in Systems Using Overlaid Memory Spaces and Write-Through Mode with
Caching Disabled During SMM................................................................................................51
Figure 38 SMM Timing in Systems Using Overlaid Memory Spaces and Configured in
Write-Back Mode......................................................................................................................51
Figure 39 CLK Waveforms ......................................................................................................................61
Figure 40 Output Valid Delay Timing ......................................................................................................61
Figure 41 Maximum Float Delay Timing ..................................................................................................62
Figure 42 PCHK Valid Delay Timing .......................................................................................................62
Figure 43 Input Setup and Hold Timing ...................................................................................................63
Figure 44 RDY and BRDY Input Setup and Hold Timing ........................................................................63
Figure 45 TCK Waveforms ......................................................................................................................64
Figure 46 Test Signal Timing Diagram ....................................................................................................64
LIST OF TABLES
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Clocking Options .......................................................................................................................1
EADS Sample Time ................................................................................................................14
Cache Line Organization .........................................................................................................19
Legal Cache Line States .........................................................................................................19
MESI Cache Line Status .........................................................................................................20
Key to Switching Waveforms ...................................................................................................22
WBINVD/INVD Special Bus Cycles .........................................................................................33
FLUSH Special Bus Cycles .....................................................................................................34
Pin State during Stop Grant Bus State ....................................................................................37
SMRAM State Save Map ........................................................................................................43
SMM Initial CPU Core Register Settings .................................................................................45
Segment Register Initial States ...............................................................................................45
SMM Revision Identifier ..........................................................................................................46
SMM Revision Identifier Bit Definitions ...................................................................................46
HALT Auto Restart Configuration ............................................................................................47
I/O Trap Word Configuration ...................................................................................................47
Test Register TR4 Bit Descriptions .........................................................................................53
Test Register TR5 Bit Descriptions .........................................................................................53
CPU ID Codes .........................................................................................................................56
CPUID Instruction Description .................................................................................................56
Thermal Resistance (°C/W)
θ
JC
and
θ
JA
for the Am5
X
86 CPU in 168-Pin PGA Package .......65
Maximum T
A
at Various Airflows in °C ....................................................................................65
Maximum T
A
for SQFP Package by Clock Frequency.............................................................65
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| AM600 | 制造商:EXTECH 制造商全稱:Extech Instruments Corporation. 功能描述:600A AC Analog Clamp Meter |
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