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參數(shù)資料
| 型號： | AM5X86 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能單片32位微處理器) |
| 中文描述： | 高性能設(shè)計(jì)的片上集成完整的32位架構(gòu)Micrprocessor（高性能單片32位微處理器） |
| 文件頁數(shù)： | 40/67頁 |
| 文件大?。?/td> | 1201K |
| 代理商： | AM5X86 |
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40
Am5
X
86 Microprocessor
AMD
context normally consists of the CPU registers that
fully represent the processor state.
I
Context Switch:
A context switch is the process of
either saving or restoring the context. The SMM dis-
cussion refers to the context switch as the process
of saving/restoring the context while invoking/exiting
SMM, respectively.
I
SMSAVE:
A mechanism that saves and restores all
internal registers to and from SMRAM.
7.3
System Management Interrupt
Processing
The system interrupts the normal program execution
and invokes SMM by generating a System Management
Interrupt (SMI) to the CPU. The CPU services the SMI
by executing the following sequence (see Figure 22).
1.
The CPU asserts the SMIACT signal, instructing the
system to enable the SMRAM.
The CPU saves its state (internal register) to SM-
RAM. It starts at the SMBASE relative address lo-
cation (see Section 7.3.3), and proceeds downward
in a stack-like fashion.
The CPU switches to the SMM processor environ-
ment (an external pseudo-real mode).
The CPU then jumps to the absolute address of
SMBASE + 8000h in SMRAM to execute the SMI
handler. This SMI handler performs the system
management activities.
Note:
If the SMRAM shares the same physical address
location with part of the system RAM, it is “overlaid”
SMRAM. To preserve cache consistency and correct
SMM operation in systems using overlaid SMRAM, the
cache must be flushed via the FLUSH pin when entering
SMM.
2.
3.
4.
5.
The SMI handler then executes the RSM instruction
which restores the CPU’s context from SMRAM,
deasserts the SMIACT signal, and then returns con-
trol to the previously interrupted program execution.
SMI
#1
#2
#3
Instr
Instr
Instr
State Save
SMI Handler
State Restore
#4
#5
Instr
Instr
SMI
SMIACT
Figure 22. Basic SMI Interrupt Service
RSM
I
Dedicated and secure memory space (SMRAM) for
SMI handler code and CPU state (context) data with
a status signal for the system to decode access to
that memory space, SMIACT
I
Resume (RSM) instruction, for exiting SMM
I
Special features, such as I/O Restart and I/O instruc-
tion information, for transparent power management
of I/O peripherals, and Auto HALT Restart
7.2
Terminology
The following terms are used throughout the discussion
of System Management mode.
I
SMM:
System Management mode. The operating
environment that the processor (system) enters
when servicing a System Management Interrupt.
I
SMI:
System Management Interrupt. This is the trig-
ger mechanism for the SMM interface. When SMI is
asserted (SMI pin asserted Low) it causes the pro-
cessor to invoke SMM. The SMI pin is the only
means of entering SMM.
I
SMI handler:
System Management mode handler.
This is the code that is executed when the processor
is in SMM. Example applications that this code might
implement are a power management control or a
system control function.
I
RSM:
Resume instruction. This instruction is used
by the SMI handler to exit the SMM and return to the
interrupted OS or application process.
I
SMRAM:
This is the physical memory dedicated to
SMM. The SMI handler code and related data reside
in this memory. The processor also uses this mem-
ory to store its context before executing the SMI han-
dler. The operating system and applications should
not have access to this memory space.
I
SMBASE:
This is a control register that contains the
base address that defines the SMRAM space.
I
Context:
This term refers to the processor state. The
SMM discussion refers to the context, or processor
state, just before the processor invokes SMM. The
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