參數(shù)資料
型號(hào)： AM5X86
廠商： Advanced Micro Devices, Inc.
英文描述： High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能單片32位微處理器)
中文描述： 高性能設(shè)計(jì)的片上集成完整的32位架構(gòu)Micrprocessor（高性能單片32位微處理器）
文件頁(yè)數(shù)： 6/67頁(yè)
文件大?。?/td> 1201K
代理商： AM5X86
6
Am5
X
86 Microprocessor
AMD
PRELIMINARY
8
Test Registers 4 and 5 Modifications ..................................................................................................53
8.1 TR4 Definition................................................................................................................................53
8.2 TR5 Definition................................................................................................................................54
8.3 Using TR4 and TR5 for Cache Testing..........................................................................................55
8.3.1 Example 1: Reading the Cache (Write-back mode only) .....................................................55
8.3.2 Example 2: Writing the Cache..............................................................................................55
8.3.3 Example 3: Flushing the Cache ...........................................................................................55
Am5
X
86 CPU Functional Differences .................................................................................................55
9.1 Status after Reset .........................................................................................................................55
9.2 Cache Status ................................................................................................................................55
9.3 CLKMUL Pin .................................................................................................................................55
10 Am5
X
86 CPU Identification .................................................................................................................56
10.1 DX Register at RESET ................................................................................................................56
10.2 CPUID Instruction .......................................................................................................................56
10.2.1 CPUID Timing ...................................................................................................................56
10.2.2 CPUID Operation ..............................................................................................................56
11 Electrical Data .....................................................................................................................................57
11.1 Power and Grounding .................................................................................................................57
11.1.1 Power Connections ...........................................................................................................57
11.1.2 Power Decoupling Recommendations ..............................................................................57
11.1.3 Other Connection Recommendations ...............................................................................57
12 Package Thermal Specifications .........................................................................................................65
13 Physical Dimensions ...........................................................................................................................66
9
LIST OF FIGURES
Figure 1
Processor-Induced Line Transitions in Write-Back mode .......................................................20
Figure 2
Snooping State Transitions .....................................................................................................21
Figure 3
Typical System Block Diagram for HOLD/HLDA Bus Arbitration ............................................22
Figure 4
External Read .........................................................................................................................23
Figure 5
External Write ..........................................................................................................................23
Figure 6
Snoop of On-Chip Cache That Does Not Hit a Line ................................................................24
Figure 7
Snoop of On-Chip Cache That Hits a Non-modified Line ........................................................24
Figure 8
Snoop That Hits a Modified Line (Write-Back) ........................................................................25
Figure 9
Write-Back and Pending Access .............................................................................................26
Figure 10 Valid HOLD Assertion During Write-Back ...............................................................................27
Figure 11 Closely Coupled Cache Block Diagram ..................................................................................28
Figure 12 Snoop Hit Cycle with Write-Back .............................................................................................29
Figure 13 Cycle Reordering with BOFF (Write-Back) ..............................................................................30
Figure 14 Write Cycle Reordering Due to Buffering ................................................................................31
Figure 15 Latest Snooping of Copy-Back ................................................................................................33
Figure 16 Burst Write ..............................................................................................................................34
Figure 17 Burst Read with BOFF Assertion ............................................................................................34
Figure 18 Burst Write with BOFF Assertion .............................................................................................35
Figure 19 Entering Stop Grant State .......................................................................................................37
Figure 20 Stop Clock State Machine .......................................................................................................38
Figure 21 Recognition of Inputs when Exiting Stop Grant State .............................................................38
Figure 22 Basic SMI Interrupt Service .....................................................................................................40
Figure 23 Basic SMI Hardware Interface..................................................................................................41
Figure 24 SMI Timing for Servicing an I/O Trap ......................................................................................41
Figure 25 SMIACT Timing .......................................................................................................................42
Figure 26 Redirecting System Memory Address to SMRAM ...................................................................42
Figure 27 Transition to and from SMM ....................................................................................................44
Figure 28 Auto HALT Restart Register Offset..........................................................................................47
Figure 29 I/O Instruction Restart Register Offset ....................................................................................47
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