參數(shù)資料
型號(hào)： AM5X86
廠商： Advanced Micro Devices, Inc.
英文描述： High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能單片32位微處理器)
中文描述： 高性能設(shè)計(jì)的片上集成完整的32位架構(gòu)Micrprocessor（高性能單片32位微處理器）
文件頁(yè)數(shù)： 52/67頁(yè)
文件大?。?/td> 1201K
代理商： AM5X86
52
Am5
X
86 Microprocessor
AMD
PRELIMINARY
7.8.4
The system designer should take into account the fol-
lowing restrictions while implementing the CPU Reset
logic:
CPU Reset During SMM
1.
When running software written for the 80286 CPU,
a CPU RESET switches the CPU from Protected
mode to Real mode. RESET and SRESET have a
higher priority than SMI. When the CPU is in SMM,
the SRESET to the CPU during SMM should be
blocked until the CPU exits SMM. SRESET must
be blocked beginning from the time when SMI is
driven active. Care should be taken not to block the
global system RESET, which may be necessary to
recover from a system crash.
During execution of the RSM instruction to exit
SMM, there is a small time window between the
deassertion of SMIACT and the completion of the
RSM microcode. If a Protected mode to Real mode
SRESET is asserted during this window, it is pos-
sible that the SMRAM space will be violated. The
system designer must guarantee that SRESET is
blocked until at least 20 CPU clock cycles after SMI-
ACT has been driven inactive or until the start of a
bus cycle.
Any request for a CPU RESET for the purpose of
switching the CPU from Protected mode to Real
mode must be acknowledged after the CPU has
exited SMM. To maintain software transparency,
the system logic must latch any SRESET signals
that are blocked during SMM.
For these reasons, the SRESET signal should be used
for any soft resets, and the RESET signal should be
used for all
hard resets.
2.
3.
7.8.5
Before the processor enters SMM, it empties its internal
write buffers. This is to ensure that the data in the write
buffers is written to normal memory space, not SMM
space. When the CPU is ready to begin writing an SMM
state save to SMRAM, it asserts SMIACT. SMIACT may
be driven active by the CPU before the system memory
controller has had an opportunity to empty the second
level write buffers.
SMM and Second Level Write Buffers
To prevent the data from these second level write buffers
from being written to the wrong location, the system
memory controller needs to direct the memory write cy-
cles to either SMM space or normal memory space. This
can be accomplished by saving the status of SMIACT
with the address for each word in the write buffers.
7.8.6
Special care must be taken when executing an SMI han-
dler for the purpose of restarting an l/O instruction. When
l/O restart slot set, the restored EIP is modified to point
to the instruction immediately preceding the SMI re-
Nested SMI and I/O Restart
quest, so that the l/O instruction can be re-executed. If
a new SMI request is received while the CPU is execut-
ing an SMI handler, the CPU services this SMI request
before restarting the original I/O instruction. If the I/O
restart slot is set when the CPU executes the RSM in-
struction for the second SMI handler, the RSM micro-
code decrements the restored EIP again. EIP then
points to an address different from the originally inter-
rupted instruction, and the CPU begins execution at an
incorrect entry point. To prevent this from occurring, the
SMI handler routine must not set the I/O restart slot
during the second of two consecutive SMI handlers.
7.9
7.9.1
The default operand size and the default address size
are 16 bits; however, operand-size override and ad-
dress-size override prefixes can be used as needed to
directly access data anywhere within the 4-Gbyte logical
address space.
SMM Software Considerations
SMM Code Considerations
With operand-size override prefixes, the SMI handler
can use jumps, calls, and returns to transfer a control
to any location within the 4-Gbyte space. Note, however,
the following restrictions:
1.
Any control transfer that does not have an operand-
size override prefix truncates EIP to 16 Low-order bits.
Due to the Real mode style of base-address formation,
a long jump or call cannot transfer control segment
with a base address of more than 20 bits (1 Mbyte).
7.9.2
Exception Handling
Upon entry into SMM, external interrupts that require
handlers are disabled (the IF in EFLAGS is cleared).
This is necessary because, while the processor is in
SMM, it is running in a separate memory space. Con-
sequently, the vectors stored in the interrupt descriptor
table (IDT) for the prior mode are not applicable. Before
allowing exception handling (or software interrupts), the
SMM program must initialize new interrupt and excep-
tion vectors. The interrupt vector table for SMM has the
same format as for Real mode. Until the interrupt vector
table is correctly initialized, the SMI handler must not
generate an exception (or software interrupt). Even
though hardware interrupts are disabled, exceptions
and software interrupts can still occur. Only a correctly
written SMI handler can prevent internal exceptions.
When new exception vectors are initialized, internal ex-
ceptions can be serviced. Restrictions are as follows:
2.
1.
Due to the Real mode style of base address forma-
tion, an interrupt or exception cannot transfer con-
trol to a segment with a base address of more than
20 bits.
An interrupt or exception cannot transfer control to
a segment offset of more than 16 bits.
If exceptions or interrupts are allowed to occur, only
the Low order 16 bits of the return address are
2.
3.
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