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參數(shù)資料
| 型號(hào)： | AM79C973VCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| 中文描述： | 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁(yè)數(shù)： | 120/304頁(yè) |
| 文件大小： | 2092K |
| 代理商： | AM79C973VCW |
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120
Am79C973/Am79C975
P R E L I M I N A R Y
PCI Capabilities Pointer Register
Offset 34h
Bit
Name
Description
7-0
CAP_PTR
The PCI Capabilities pointer
Register is an 8-bit register that
points to a linked list of capabili-
ties implemented on this device.
This register has a default value
of 40h.
The PCI Capabilities register is
located at offset 34h in the PCI
Configuration Space. It is read
only.
PCI Interrupt Line Register
Offset 3Ch
The PCI Interrupt Line register is an 8-bit register that
is used to communicate the routing of the interrupt.
This register is written by the POST software as it ini-
tializes the Am79C973/Am79C975 controller in the
system. The register is read by the network driver to
determine the interrupt channel which the POST soft-
ware has assigned to the Am79C973/Am79C975 con-
troller. The PCI Interrupt Line register is not modified by
the Am79C973/Am79C975 controller. It has no effect
on the operation of the device.
The PCI Interrupt Line register is located at offset 3Ch
in the PCI Configuration Space. It is read and written by
the host. It is cleared by H_RESET and is not affected
by S_RESET or by setting the STOP bit.
PCI Interrupt Pin Register
Offset 3Dh
This PCI Interrupt Pin register is an 8-bit register that
indicates the interrupt pin that the Am79C973/
Am79C975 controller is using. The value for the
Am79C973/Am79C975 Interrupt Pin register is 01h,
which corresponds to INTA.
The PCI Interrupt Pin register is located at offset 3Dh
in the PCI Configuration Space. It is read only.
PCI MIN_GNT Register
Offset 3Eh
The PCI MIN_GNT register is an 8-bit register that
specifies the minimum length of a burst period that the
Am79C973/Am79C975 device needs to keep up with
the network activity. The length of the burst period is
calculated assuming a clock rate of 33 MHz. The regis-
ter value specifies the time in units of 1/4 ms. The PCI
MIN_GNT register is an alias of BCR22, bits 7-0. It is
recommended that the BCR22 be programmed to a
value of 1818h.
The host should use the value in this register to deter-
mine the setting of the PCI Latency Timer register.
The PCI MIN_GNT register is located at offset 3Eh in
the PCI Configuration Space. It is read only.
PCI MAX_LAT Register
Offset 3Fh
The PCI MAX_LAT register is an 8-bit register that spec-
ifies the maximum arbitration latency the Am79C973/
Am79C975 controller can sustain without causing prob-
lems to the network activity. The register value specifies
the time in units of 1/4 μs. The MAX_LAT register is an
alias of BCR22, bits 15-8. It is recommended that
BCR22 be programmed to a value of 1818h.
The host should use the value in this register to deter-
mine the setting of the PCI Latency Timer register.
The PCI MAX_LAT register is located at offset 3Fh in
the PCI Configuration Space. It is read only
PCI Capability Identifier Register
Offset 40h
Bit
Name
Description
7-0
CAP_ID
This register, when set to 1, iden-
tifies the linked list item as being
the PCI Power Management reg-
isters. This register has a default
value of 1h.
The PCI Capabilities Identifier
register is located at offset 40h in
the PCI Configuration Space. It is
read only.
PCI Next Item Pointer Register
Offset 41h
Bit
Name
Description
7-0
NXT_ITM_PTR
The Next Item Pointer Register
points to the starting address of
the next capability. The pointer at
this offset is a null pointer, indi-
cating that this is the last capabil-
ity in the linked list of the
capabilities. This register has a
default value of 0h.
The PCI Next Pointer Register is
located at offset 41h in the PCI
Configuration Space. It is read
only.
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| AM79C974 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
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