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參數(shù)資料
| 型號： | AM79C973VCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| 中文描述： | 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁數(shù)： | 252/304頁 |
| 文件大?。?/td> | 2092K |
| 代理商： | AM79C973VCW |
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252
Am79C973/Am79C975
P R E L I M I N A R Y
network. Any value above 128 will create unpredictable
results. Padding is not supported by the SMIU.
Once the Transmit Data memory is filled with the data
of the alert frame and the Transmit Message Length
register is setup with the length of the alert frame, the
host must set the MTX_START bit in the Transmit Sta-
tus register to start the transmission. The Am79C975
controller will transmit the alert frame after any pending
frame transmission (including retries) has completed.
The host can poll the MTX_DONE bit in the Interrupt
register to determine if the transmission of the alert
frame has already ended. The MTX_DONE bit will be
set to a 1 after the end of transmission, independent of
the success of the operation. The MTX_DONE bit will
auto-clear after reading the Interrupt register.
The MTX_ADR register is cleared by setting the
MTX_START bit. The host must not load data for a new
alert frame into the Transmit Data memory until the
transmission of the current frame is ended as indicated
by the MTX_DONE bit. It is possible to issue a new
MTX_START command without loading new data to
the Transmit Data memory or updating the MTX_LEN
register.
The Am79C975 controller provides an asynchronous
interrupt pin to signal the host that the transmission of
the alert frame is complete. After the end of the trans-
mission, the MIRQ pin will be asserted, if the global in-
terrupt enable bit MIRQEN in the Command register is
set to a 1 and the transmit interrupt mask bit
(MTX_DONEM) is cleared to 0 (default state). Once
MIRQ is asserted, the host can read the MTX_DONE
bit in the Interrupt register to determine that the inter-
rupt was caused by the end of the transmission. The
read of the Interrupt register will clear the MTX_DONE
bit and cause the deassertion of the MIRQ pin. The In-
terrupt register also provides a global interrupt bit
MIRQ that is the OR of the MTX_DONE and
MRX_DONE bits.
Once the MTX_DONE bit indicates that the transmis-
sion of the alert frame has ended, MTX_START is
cleared and the SMIU Transmit Status register provides
the error status for the transmission. Three error condi-
tions are reported: Late Collision, Loss of Carrier and
Retry Error. There is also an error summary bit
(MTX_ERR). The transmit status bits remain valid as
long as the MTX_START bit is set to 0.
The Transmit Retry Error condition requires special at-
tention. It can happen, that the START or STOP bit is
set in the Am79C975 controller to change normal oper-
ation. START and STOP cause a reset of the transmit
logic. Normal transmission of an alert frame will suc-
ceed. If, however, the SMIU is in the middle of a backoff
interval or the transmission of the alert frame is suffer-
ing a collision, the transmission will abort and the
MTX_RTRY bit will be set. If MTX_RTRY is set in the
SMIU Transmit Status register, the host should re-
transmit the frame.
Receive Operation
The System Management Interface Unit (SMIU) of the
Am79C975 controller provides a separate 128-byte
Receive Data memory to store an incoming manage-
ment or acknowledgment frame. The normal receive
address matching mechanism (physical address, logi-
cal address, broadcast address) of the MAC cannot be
used by the SMIU. The Am79C975 controller provides
an Acknowledgment Frame Filter instead. The filter is
stored in a 40-byte Receive Pattern RAM.
The Receive Pattern RAM is organized as 8 pattern
words of 5 bytes each. Each pattern word holds four
bytes of data to be compared with the incoming frame
plus mask information that indicates which bytes
should be included in the comparison. The pattern
word also contains a field that indicates how many
Dwords of the incoming frame should be skipped be-
fore this Dword of pattern is compared with frame data.
This field makes it unnecessary to store data for long
series of bytes that will be excluded from the compari-
son anyway. A maximum of 7 Dwords (28 bytes) can be
skipped. If the filter pattern contains a string of more
than 7 Dwords that must be excluded from the compar-
ison, one or more pattern words will be loaded with the
value 7h in the Skip field and 0h in the Mask field. Fi-
nally the most significant bit of the pattern word indi-
cates whether or not this word is the end of the stored
pattern.
The format of the pattern words is shown below.
Bits
Name
Description
31:0
Pattern
Bytes of data to be compared with the incoming frame. The least significant byte corresponds to the
first byte of the Dword received from the network.
35:32
Mask
Bits 3:0 of this field correspond to bytes 3:0 of the pattern field. If bit n of this field is 0, byte n of the
pattern is ignored in the comparison.
38:36
Skip
This field indicates how many Dwords of the incoming frame must be skipped before the pattern in this
word is compared with data from the incoming frame. A maximum of 7 Dwords may be skipped per
pattern word.
39
EOP
End of Pattern. If this bit is set, this pattern word contains the last Dword of the frame filter.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AM79C974 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
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