- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366551 > AM79C973VCW (ADVANCED MICRO DEVICES INC) PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C973VCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| 中文描述： | 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁(yè)數(shù)： | 249/304頁(yè) |
| 文件大?。?/td> | 2092K |
| 代理商： | AM79C973VCW |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)當(dāng)前第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)第275頁(yè)第276頁(yè)第277頁(yè)第278頁(yè)第279頁(yè)第280頁(yè)第281頁(yè)第282頁(yè)第283頁(yè)第284頁(yè)第285頁(yè)第286頁(yè)第287頁(yè)第288頁(yè)第289頁(yè)第290頁(yè)第291頁(yè)第292頁(yè)第293頁(yè)第294頁(yè)第295頁(yè)第296頁(yè)第297頁(yè)第298頁(yè)第299頁(yè)第300頁(yè)第301頁(yè)第302頁(yè)第303頁(yè)第304頁(yè)
Am79C973/Am79C975
249
P R E L I M I N A R Y
of the Block Write command specifies the byte count.
The byte count value is ignored by the Am79C975 con-
troller. The device is capable of receiving any amount
of data even passed the limit of 32 bytes as defined by
the SMB specification. Since the Am79C975 controller
is the receiver of all data transfers, it must acknowledge
each byte by driving the MDATA line LOW for 1 bit time
(A). The master indicates the termination of the Block
Write command with the assertion of the STOP condi-
tion (P).
Note that the Am79C975 controller does not validate
the register address specified in the Block Write com-
mand. A Block Write command to a register other than
the Transmit Data port or the Receive Pattern RAM
Data port may cause unexpected reprogramming of an
SMIU register. The Am79C975 controller also does not
check the length of the Block Write command. The
master must make sure that the Transmit Data memory
or the Receive Pattern RAM are not written beyond
their respective length.
Key:
Figure 74. Block Write Command
Block Read Command
The Block Read command is used to read data from
the SMIU Receive Data memory. This command is
more complex compared to the Block Write command,
since it involves a change in the direction of the data
transfer. The command starts with the START condition
(S). The next 7 bits are the slave address of the
Am79C975 controller, followed by a 0 bit to indicate that
the data transfer starts with a write operation from the
master to the Am79C975 controller (W). The
Am79C975 controller must acknowledge the first byte
by driving MDATA LOW for 1 bit time (A). The next byte
specifies the address of the SMIU register (MReg) that
is accessed, followed by another ACK from the
Am79C975 controller. The address of the Receive
Data port (40), is the only valid value for the MReg ad-
dress. The master initiates the turn-around of the trans-
fer direction by asserting a repeated START condition,
followed by the repeated 7-bit slave address. This time,
the Read/Write bit is set to 1 to indicate that the next
bytes of data are driven by the Am79C975 controller
(R). The Am79C975 controller acknowledges the
transfer and then continues driving the MDATA line.
The first byte is the byte count indicating how many
bytes of data will follow. The byte count field will indi-
cate 32 in all but the last transaction, in which the byte
count field will indicate the remaining bytes of the
frame. This time, the ACK is generated by the master,
since he is the receiver of the data. Receive data will
follow. Being the receiver, the master must ACK each
byte by driving the MDATA line LOW for 1 bit time. The
last byte, however, must be followed by a NACK (N) to
force the Am79C975 controller to stop driving the
MDATA line. The Am79C975 device is capable of a
block read past the 32 byte limit that is indicated in the
byte count field. If the host does not assert NACK after
the 32
nd
byte, the Am79C975 controller will continue
driving receive data onto the MDATA line until the host
asserts NACK. If the master runs out of storage space
for the incoming data, he can abort the data transfer
after any byte by asserting NACK. The Block Read
command terminates with the assertion of the STOP
condition (P) by the master.
Note:
The Am79C975 controller does not validate the
register address specified in the Block Read command.
A Block Read command to a register other than the Re-
ceive Data port will yield unexpected data. The master
must also make sure to only issue a Block Read com-
mand when there is data left in the Receive Data mem-
ory.
1
7
1
1
8
1
8
1
S
Slave Address
W
A
MReg Address
A
Byte Count N
A
8
1
8
1
1
Data Byte 1
A
…
.
Data Byte N
A
P
Master to Am79C975 controller
Am79C975 controller to Master
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C975VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C976 | PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
| AM79C976KIW | PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
| AM79C976KCW | PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
| AM79C978AKCW | Single-Chip 1/10 Mbps PCI Home Networking Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C974 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| AM79C974KC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C974KC/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C974KCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。