參數(shù)資料
型號(hào)： AM79C973VCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
中文描述： 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176
封裝： TQFP-176
文件頁(yè)數(shù)： 127/304頁(yè)
文件大?。?/td> 2092K
代理商： AM79C973VCW
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Am79C973/Am79C975
127
P R E L I M I N A R Y
Bit
31-16
Name
RES
Description
Reserved locations. Written as
zeros and read as undefined.
15-13
RES
Reserved locations. Read and
written as zero.
12
MISSM
Missed Frame Mask. If MISSM is
set, the MISS bit will be masked
and unable to set the INTR bit.
Read/Write accessible always.
MISSM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
11
MERRM
Memory Error Mask. If MERRM
is set, the MERR bit will be
masked and unable to set the
INTR bit.
Read/Write accessible always.
MERRM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
10
RINTM
Receive Interrupt Mask. If RINTM
is set, the RINT bit will be masked
and unable to set the INTR bit.
Read/Write accessible always.
RINTM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
9
TINTM
Transmit
TINTM is set, the TINT bit will be
masked and unable to set the
INTR bit.
Interrupt
Mask.
If
Read/Write accessible always.
TINTM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
8
IDONM
Initialization
IDONM is set, the IDON bit will be
masked and unable to set the
INTR bit.
Done
Mask.
If
Read/Write accessible always.
IDONM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
7
RES
Reserved location. Read and
written as zeros.
6
DXSUFLO
Disable Transmit Stop on Under-
flow error.
When DXSUFLO (CSR3, bit 6) is
set to 0, the transmitter is turned
off when an UFLO error occurs
(CSR0, TXON = 0).
When DXSUFLO is set to 1, the
Am79C973/Am79C975 controller
gracefully recovers from an
UFLO error. It scans the transmit
descriptor ring until it finds the
start of a new frame and starts a
new transmission.
Read/Write accessible always.
DXSUFLO
is
H_RESET or S_RESET and is
not affected by STOP.
cleared
by
5
LAPPEN
Look Ahead Packet Processing
Enable. When set to a 1, the
LAPPEN bit will cause the
Am79C973/Am79C975 controller
to generate an interrupt following
the descriptor write operation to
the first buffer of a receive frame.
This interrupt will be generated in
addition to the interrupt that is
generated following the descrip-
tor write operation to the last buff-
er of a receive packet. The
interrupt will be signaled through
the RINT bit of CSR0.
Setting LAPPEN to a 1 also en-
ables the Am79C973/Am79C975
controller to read the STP bit of
receive
descriptors.
Am79C973/Am79C975 controller
will use the STP information to
determine where it should begin
writing a receive packet
’
s data.
Note that while in this mode, the
Am79C973/Am79C975 controller
can write intermediate packet
data to buffers whose descriptors
do not contain STP bits set to 1.
Following the write to the last de-
scriptor used by a packet, the
Am79C973/Am79C975 controller
will scan through the next de-
scriptor entries to locate the next
STP bit that is set to a 1. The
Am79C973/Am79C975 controller
will begin writing the next packets
data to the buffer pointed to by
that descriptor.
The
Note that because several de-
scriptors may be allocated by the
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