參數(shù)資料
型號(hào)： AM79C973VCW
廠商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： 微控制器/微處理器
英文描述： PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
中文描述： 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176
封裝： TQFP-176
文件頁(yè)數(shù)： 154/304頁(yè)
文件大?。?/td> 2092K
代理商： AM79C973VCW
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154
Am79C973/Am79C975
P R E L I M I N A R Y
setting of the MERRM bit (CSR3,
bit 11) and the IENA bit (CSR0,
bit 6).
The value in this register is inter-
preted as the unsigned number of
bus clock periods divided by two,
(i.e., the value in this register is
given in 0.1 ms increments.) For
example, the value 0600h (1536
decimal) will cause a MERR to be
indicated after 153.6 ms of bus
latency. A value of 0 will allow an
infinitely long bus latency, i.e.,
bus timeout error will never oc-
cur.
Read/Write accessible only when
either the STOP or the SPND bit
is set. This register is set to
0600h
by
S_RESET and is unaffected by
STOP.
H_RESET
or
CSR112: Missed Frame Count
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
MFC
Missed Frame Count. Indicates
the number of missed frames.
MFC will roll over to a count of 0
from the value 65535. The MFCO
bit of CSR4 (bit 8) will be set each
time that this occurs.
Read accessible always. MFC is
read only, write operations are ig-
nored. MFC is cleared by
H_RESET or S_RESET or by
setting the STOP bit.
CSR114: Receive Collision Count
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
RCC
Receive Collision Count. Indi-
cates the total number of colli-
sions
encountered
receiver since the last reset of the
counter.
by
the
RCC will roll over to a count of 0
from the value 65535. The
RCVCCO bit of CSR4 (bit 5) will
be set each time that this occurs.
Read accessible always. RCC is
read only, write operations are ig-
nored. RCC is cleared by
H_RESET or S_RESET, or by
setting the STOP bit.
CSR116: OnNow Power Mode Register
Note:
Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
Description
31-14 RES
Reserved locations. Written as
zeros and read as undefined.
13 LCMODE_D3C. This bit is a read/write from the
PCI bus and is reset only at
power-on. This bit is not written
from the EEPROM. Power man-
agement software can set this bit
before going to D3cold and even
if there is a reset and the EE-
PROM loads because of an incor-
rect PG signal, the control bit will
not be changed. This bit is OR
’
ed
with LCMODE (CSR116 bit 8) for
OnNow link chnage, but not for
hardware link change
12 MPPEN_D3C
This bit is read/write from the the
PCI bus and is reset only at
power-on. This bit is not written
from the EEPROM. Power man-
agement software can set this bit
before going to D3cold and even
if there is a reset and the EE-
PROM loads because of an incor-
rect PG signal, the control bit will
not be changed. This bit is OR
’
ed
with MPPEN (CSR116 bit 4) for
both hardware magic packet or
OnNow magic packet.
11 PMAT_MODE_D3C
This bit is read/write from the the
PCI bus and is reset only at
power-on. This bit is not written
from the EEPROM. Power man-
agement software can set this bit
before going to D3cold and even
if there is a reset and the EE-
PROM loads because of an incor-
rect PG signal, the control bit will
not be changed. This bit is OR
’
ed
with PMAT_MODE (BCR45 bit 7)
for OnNow magic packet.
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