122
Am79C973/Am79C975
P R E L I M I N A R Y
Read/write accessible always.
Sticky bit. This bit is reset by
POR. H_RESET, S_RESET, or
setting the STOP bit has no ef-
fect.
14-13 DATA_SCALE
Data Scale. This two bit read-
only field indicates the scaling
factor to be used when interpret-
ing the value of the Data register.
The value and meaning of this
field will vary depending on the
DATA_SCALE field.
Read only.
12-9
DATA_SEL Data Select. This optional four-bit
field is used to select which data
is reported through the Data reg-
ister and DATA_SCALE field.
Read/write accessible always.
Sticky bit. This bit is reset by
POR. H_RESET, S_RESET, or
setting the STOP bit has no ef-
fect.
8
PME_EN
PME
PME_EN enables the function to
assert PME. When a 0, PME as-
sertion is disabled.
Enable.
When
a
1,
This bit defaults to
“
0
”
if the func-
tion does not support PME gener-
ation from D3cold.
If the function supports PME from
D3cold, then this bit is sticky and
must be explicitly cleared by the
operating system each time the
operating system is initially load-
ed.
Read/write accessible always.
Sticky bit. This bit is reset by
POR. H_RESET, S_RESET, or
setting the STOP bit has no ef-
fect.
7-2
RES
Reserved locations. Read only.
1-0
PWR_STATE Power State. This 2-bit field is
used both to determine the cur-
rent power state of a function and
to set the function into a new
power state. The definition of the
field values is given below.
00b - D0.
01b - D1.
10b - D2.
11b - D3.
These bits can be written and
read, but their contents have no
effect on the operation of the de-
vice.
Read/write accessible always.
PCI PMCSR Bridge Support Extensions Register
Offset 46h
Bit
Name
Description
7-0
PMCSR_BSE The PCI PMCSR Bridge Support
Extensions Register is an 8-bit
register. PMCSR Bridge Support
Extensions are not supported.
This register has a default value
of 00h.
The PCI PMCSR Bridge Support
Extensions register is located at
offset 46h in the PCI Configura-
tion Space. It is read only.
PCI Data Register
Offset 47h
Note:
All bits of this register are loaded from EE-
PROM. The register is aliased to lower bytes of the
BCR37-44 for testing purposes.
Bit
Name
Description
7-0
DATA_REG The PCI Data Register is an 8-bit
register. Refer to the
“
PCI Bus
Power Management Interface
Specification
”
version 1.1 for a
more detailed description of this
register.
The PCI DATA register is located
at offset 47h in the PCI Configu-
ration Space. It is read only.
RAP Register
The RAP (Register Address Pointer) register is used to
gain access to CSR and BCR registers on board the
Am79C973/Am79C975 controller. The RAP contains
the address of a CSR or BCR.
As an example of RAP use, consider a read access to
CSR4. In order to access this register, it is necessary
to first load the value 0004h into the RAP by performing
a write access to the RAP offset of 12h (12h when WIO
mode has been selected, 14h when DWIO mode has