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參數(shù)資料
| 型號(hào)： | AM79C973VCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| 中文描述： | 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁(yè)數(shù)： | 29/304頁(yè) |
| 文件大?。?/td> | 2092K |
| 代理商： | AM79C973VCW |
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Am79C973/Am79C975
29
P R E L I M I N A R Y
PIN DESCRIPTIONS
PCI Interface
AD[31:0]
Address and Data
Address and data are multiplexed on the same bus inter-
face pins. During the first clock of a transaction, AD[31:0]
contain a physical address (32 bits). During the subse-
quent clocks, AD[31:0] contain data. Byte ordering is little
endian by default. AD[7:0] are defined as the least signifi-
cant byte (LSB) and AD[31:24] are defined as the most
significant byte (MSB). For FIFO data transfers, the
Am79C973/Am79C975 controller can be programmed for
big endian byte ordering. See CSR3, bit 2 (BSWP) for
more details.
Input/Output
During the address phase of the transaction, when the
Am79C973/Am79C975 controller is a bus master,
AD[31:2] will address the active Double Word (DWord).
The Am79C973/Am79C975 controller always drives
AD[1:0] to
’
00
’
during the address phase indicating linear
burst order. When the Am79C973/Am79C975 controller is
not a bus master, the AD[31:0] lines are continuously
monitored to determine if an address match exists for
slave transfers.
During the data phase of the transaction, AD[31:0] are
driven by the Am79C973/Am79C975 controller when per-
forming bus master write and slave read operations. Data
on AD[31:0] is latched by the Am79C973/Am79C975 con-
troller when performing bus master read and slave write
operations.
When RST is active, AD[31:0] are inputs for NAND tree
testing.
C/BE[3:0]
Bus Command and Byte Enables
Input/Output
Bus command and byte enables are multiplexed on the
same bus interface pins. During the address phase of the
transaction, C/BE[3:0] define the bus command. During
the data phase, C/BE[3:0] are used as byte enables. The
byte enables define which physical byte lanes carry mean-
ingful data. C/BE0 applies to byte 0 (AD[7:0]) and C/BE3
applies to byte 3 (AD[31:24]). The function of the byte en-
ables is independent of the byte ordering mode (BSWP
CSR3, bit 2).
When RST is active, C/BE[3:0] are inputs for NAND tree
testing
.
CLK
Clock
This clock is used to drive the system bus interface and
the internal buffer management unit. All bus signals are
sampled on the rising edge of CLK and all parameters are
defined with respect to this edge. The Am79C973/
Input
Am79C975 controller normally operates over a frequency
range of 10 to 33 MHz on the PCI bus due to networking
demands. See the
Frequency Demands for Network Op-
eration
section for details. The Am79C973/Am79C975
controller will support a clock frequency of 0 MHz after
certain precautions are taken to ensure data integrity. This
clock or a derivation is not used to drive any network func-
tions.
When RST is active, CLK is an input for NAND tree test-
ing
.
DEVSEL
Device Select
Output
The Am79C973/Am79C975 controller drives DEVSEL
when it detects a transaction that selects the device as a
target. The device samples DEVSEL to detect if a target
claims a transaction that the Am79C973/Am79C975 con-
troller has initiated.
Input/
When RST is active, DEVSEL is an input for NAND tree
testing
.
FRAME
Cycle Frame
FRAME is driven by the Am79C973/Am79C975 controller
when it is the bus master to indicate the beginning and du-
ration of a transaction. FRAME is asserted to indicate a
bus transaction is beginning. FRAME is asserted while
data transfers continue. FRAME is deasserted before the
final data phase of a transaction. When the Am79C973/
Am79C975 controller is in slave mode, it samples FRAME
to determine the address phase of a transaction.
Input/Output
When RST is active, FRAME is an input for NAND tree
testing
.
GNT
Bus Grant
This signal indicates that the access to the bus has been
granted to the Am79C973/Am79C975 controller.
Input
The Am79C973/Am79C975 controller supports bus park-
ing. When the PCI bus is idle and the system arbiter as-
serts GNT without an active REQ from the Am79C973/
Am79C975 controller, the device will drive the AD[31:0],
C/BE[3:0] and PAR lines.
When RST is active, GNT is an input for NAND tree test-
ing
.
IDSEL
Initialization Device Select
This signal is used as a chip select for the Am79C973/
Am79C975 controller during configuration read and write
transactions.
Input
When RST is active, IDSEL is an input for NAND tree
testing.
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