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參數(shù)資料
| 型號(hào)： | AM79C973VCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| 中文描述： | 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁(yè)數(shù)： | 269/304頁(yè) |
| 文件大?。?/td> | 2092K |
| 代理商： | AM79C973VCW |
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Am79C973/Am79C975
269
P R E L I M I N A R Y
MII Receive Interface
The MII receive clock is also generated by the external
PHY and is sent to the Am79C973/Am79C975 control-
ler on the RX_CLK input pin. The clock will be the same
frequency as the TX_CLK but will be out of phase and
can run at 25 MHz or 2.5 MHz, depending on the speed
of the network to which the external PHY is attached.
The RX_CLK is a continuous clock during the reception
of the frame, but can be stopped for up to two RX_CLK
periods at the beginning and the end of frames, so that
the external PHY can sync up to the network data traffic
necessary to recover the receive clock. During this
time, the external PHY may switch to the TX_CLK to
maintain a stable clock on the receive interface. The
Am79C973/Am79C975 controller will handle this situa-
tion with no loss of data. The data is a nibble-wide (4
bits) data path, RXD(3:0), from the external PHY to the
Am79C973/Am79C975 controller and is synchronous
to the rising edge of RX_CLK.
The receive process starts when RX_DV is asserted.
RX_DV will remain asserted until the end of the receive
frame. The Am79C973/Am79C975 controller requires
CRS (Carrier Sense) to toggle in between frames in
order to receive them properly. Errors in the currently
received frame are signaled across the MII by the
RX_ER pin. RX_ER can be used to signal special con-
ditions
out of band
when RX_DV is not asserted. Two
defined out-of-band conditions for this are the
100BASE-TX signaling of
bad
Start of Frame Delimiter
and the 100BASE-T4 indication of illegal code group
before the receiver has
synched
to the incoming data.
The Am79C973/Am79C975 controller will not respond
to these conditions. All
out of band
conditions are cur-
rently treated as NULL events. Certain
in band
non-
IEEE 802.3u-compliant flow control sequences may
cause erratic behavior for the Am79C973/Am79C975
controller. Consult the switch/bridge/router/hub manual
to disable the
in-band
flow control sequences if they
are being used.
MII Network Status Interface
The MII also provides signals that are consistent and
necessary for IEEE 802.3 and IEEE 802.3u operation.
These signals are CRS (Carrier Sense) and COL (Col-
lision Sense). Carrier Sense is used to detect non-idle
activity on the network. Collision Sense is used to indi-
cate that simultaneous transmission has occurred in a
half-duplex network.
MII Management Interface
The MII provides a two-wire management interface so
that the Am79C973/Am79C975 controller can control
and receive status from external PHY devices.
The Am79C973/Am79C975 controller can support up
to 31 external PHYs attached to the MII Management
Interface with software support and only one such de-
vice without software support.
The Network Port Manager copies the PHYADD after
the Am79C973/Am79C975 controller reads the EE-
PROM and uses it to communicate with the external
PHY. The PHY address must be programmed into the
EEPROM prior to starting the Am79C973/Am79C975
controller. This is necessary so that the internal man-
agement controller can work autonomously from the
software driver and can always know where to access
the external PHY. The Am79C973/Am79C975 control-
ler is unique by offering direct hardware support of the
external PHY device without software support. The
PHY address of 1Fh is reserved and should not be
used. To access the 31 external PHYs, the software
driver must have knowledge of the external PHY
’
s ad-
dress when multiple PHYs are present before attempt-
ing to address it.
The MII Management Interface uses the MII Control,
Address, and Data registers (BCR32, 33, 34) to control
and communicate to the external PHYs. The
Am79C973/Am79C975 controller generates MII man-
agement frames to the external PHY through the MDIO
pin synchronous to the rising edge of the Management
Data Clock (MDC) based on a combination of writes
and reads to these registers.
MII Management Frames
MII management frames are automatically generated
by the Am79C973/Am79C975 controller and conform
to the MII clause in the IEEE 802.3u standard.
The start of the frame is a preamble of 32 ones and
guarantees that all of the external PHYs are synchro-
nized on the same interface. See Figure C-78. Loss of
synchronization is possible due to the
hot-plugging
ca-
pability of the exposed MII.
The IEEE 802.3 specification allows you to drop the
preamble, if after reading the MII Status Register from
the external PHY you can determine that the external
PHY will support Preamble Suppression (BCR34, bit
6). After having a valid MII Status Register read, the
Am79C973/Am79C975 controller will then drop the
creation of the preamble stream until a reset occurs, re-
ceives a read error, or the external PHY is discon-
nected.
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