參數(shù)資料
型號: AM79C973VCW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
中文描述: 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176
封裝: TQFP-176
文件頁數(shù): 96/304頁
文件大?。?/td> 2092K
代理商: AM79C973VCW
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁當(dāng)前第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁第265頁第266頁第267頁第268頁第269頁第270頁第271頁第272頁第273頁第274頁第275頁第276頁第277頁第278頁第279頁第280頁第281頁第282頁第283頁第284頁第285頁第286頁第287頁第288頁第289頁第290頁第291頁第292頁第293頁第294頁第295頁第296頁第297頁第298頁第299頁第300頁第301頁第302頁第303頁第304頁
96
Am79C973/Am79C975
P R E L I M I N A R Y
SRAM Configuration
The Am79C973/Am79C975 controller supports inter-
nal SRAM as a FIFO extension as well as providing a
read/write data path to the SRAM. The Am79C973/
Am79C975 controller contains 12 Kbytes of SRAM.
Internal SRAM Configuration
The SRAM_SIZE (BCR25, bits 7-0) programs the size
of the SRAM. SRAM_SIZE can be programmed to a
smaller value than 12 Kbytes.
The SRAM should be programmed on a 512-byte
boundary. However, there should be no accesses to the
RAM space while the Am79C973/Am79C975 control-
ler is running. The Am79C973/Am79C975 controller
assumes that it completely owns the SRAM while it is
in operation. To specify how much of the SRAM is allo-
cated to transmit and how much is allocated to receive,
the user should program SRAM_BND (BCR26, bits 7-
0) with the page boundary where the receive buffer be-
gins. The SRAM_BND also should be programmed on
a 512-byte boundary. The transmit buffer space starts
at 0000h. It is up to the user or the software driver to
split up the memory for transmit or receive; there is no
defaulted value. The minimum SRAM size required is
four 512-byte pages for each transmit and receive
queue, which limits the SRAM size to be at least 4
Kbytes.
The SRAM_BND upon H_RESET will be reset to
0000h. The Am79C973/Am79C975 controller will not
have any transmit buffer space unless SRAM_BND is
programmed. The last configuration parameter neces-
sary is the clock source used to control the Expansion
Bus interface. This is programmed through the SRAM
Interface Control register. The externally driven Expan-
sion Bus Clock (EBCLK) can be used by specifying a
value of 010h in EBCS (BCR27, bits 5-3). This allows
the user to utilize any clock that may be available.
There are two standard clocks that can be chosen as
well, the PCI clock or the externally provided time base
clock. When the PCI or time base clock is used, the
EBCLK does not have to be driven, but it must be tied
to VDD through a resistor. The user must specify an
SRAM clock (BCR27, bits 5-3) that will not stop unless
the Am79C973/Am79C975 controller is stopped. Oth-
erwise, the Am79C973/Am79C975 controller will re-
port buffer overflows, underflows, corrupt data, and will
hang eventually.
The user can decide to use a fast clock and then divide
down the frequency to get a better duty-cycle if re-
quired. The choices are a divide by 2 or 4 and is pro-
grammed by the CLK_FAC bits (BCR27, bits 2-0). Note
that the Am79C973/Am79C975 controller does not
support an SRAM frequency above 33 MHz regardless
of the clock and clock factor used.
No SRAM Configuration
If the SRAM_SIZE (BCR25, bits 7-0) value is 0 in the
SRAM size register, the Am79C973/Am79C975 con-
troller will assume that there is no SRAM present and
will reconfigure the four internal FIFOs into two FIFOs,
one for transmit and one for receive. The FIFOs will op-
erate the same as in the PCnet-PCI II controller. When
the SRAM SIZE (BCR25, bits 7-0) value is 0, the SRAM
BND (BCR26, bits 7-0) are ignored by the Am79C973/
Am79C975 controller. See Figure 46.
Low Latency Receive Configuration
If the LOLATRX (BCR27, bit 4) bit is set to 1, then the
Am79C973/Am79C975 controller will configure itself
for a low latency receive configuration. In this mode,
SRAM is required at all times. If the SRAM_SIZE
(BCR25, bits 7-0) value is 0, the Am79C973/
Am79C975 controller will not configure for low latency
receive mode. The Am79C973/Am79C975 controller
will provide a fast path on the receive side bypassing
the SRAM. All transmit traffic will go to the SRAM, so
SRAM_BND (BCR26, bits 7-0) has no meaning in low
latency receive mode. When the Am79C973/
Am79C975 controller has received 16 bytes from the
network, it will start a DMA request to the PCI Bus In-
terface Unit. The Am79C973/Am79C975 controller will
not wait for the first 64 bytes to pass to check for colli-
sions in Low Latency Receive mode. The Am79C973/
Am79C975 controller must be in STOP before switch-
ing to this mode. See Figure 47.
CAUTION: To provide data integrity when switching
into and out of the low latency mode, DO NOT SET
the FASTSPNDE bit when setting the SPND bit. Re-
ceive frames WILL be overwritten and the
Am79C973/Am79C975 controller may give erratic
behavior when it is enabled again.
Direct SRAM Access
The SRAM can be accessed through the Expansion
Bus Data port (BCR30). To access this data port, the
user must load the upper address EPADDRU (BCR29,
bits 3-0) and set FLASH (BCR29, bit 15) to 0. Then the
user will load the lower 16 bits of address EPADDRL
(BCR28, bits 15-0). To initiate a read, the user reads
the Expansion Bus Data Port (BCR30). This slave ac-
cess from the PCI will result in a retry for the very first
access. Subsequent accesses may give a retry or not,
depending on whether or not the data is present and
valid. The direct SRAM access uses the same FLASH/
EPROM access except for accessing the SRAM in
word format instead of byte format. This access is
meant to be a diagnostic access only. The SRAM can
only be accessed while the Am79C973/Am79C975
controller is in STOP or SPND (FASTSPNDE is set to
0) mode.
相關(guān)PDF資料
PDF描述
AM79C975VCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C976 PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
AM79C976KIW PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
AM79C976KCW PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
AM79C978AKCW Single-Chip 1/10 Mbps PCI Home Networking Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C974 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
AM79C974KC 制造商:Advanced Micro Devices 功能描述:
AM79C974KC/W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
AM79C974KCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems