(SCL2
參數(shù)資料
型號： APMOTOR56F8000E
廠商： Freescale Semiconductor
文件頁數(shù)： 36/124頁
文件大?。?/td> 0K
描述： KIT DEMO MOTOR CTRL SYSTEM
標(biāo)準(zhǔn)包裝： 1
附件類型： 電機(jī)控制器
適用于相關(guān)產(chǎn)品： DEMO56F8013，DEMO56F8013-E
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DEMO56F8014-EE-ND - BOARD DEMO FOR 56F8014
DEMO56F8013-EE-ND - BOARD DEMO FOR 56F8013
MC56F8014VFAE-ND - IC DIGITAL SIGNAL CTRLR 32-LQFP
MC56F8013VFAE-ND - IC DIGITAL SIGNAL CTLR 32-LQFP
更多...
56F8014 Signal Pins
56F8014 Technical Data, Rev. 11
Freescale Semiconductor
19
GPIOB7
(TXD)
(SCL2)
2
Input/
Output
Input/
Output
Input/
Output
Input with
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Transmit Data — SCI transmit data output or transmit / receive in
single wire opeation.
Serial Clock — This pin serves as the I2C serial clock.
After reset, the default state is GPIOB7. The alternative peripheral
functionality is controlled via the SIM. See Section 6.3.8.
2. This signal is also brought out on the GPIOB0 pin.
RESET
(GPIOA7)
16
Input
Input/Open
Drain
Output
Input with
internal
pull-up
enabled
Reset — This input is a direct hardware reset on the processor.
When RESET is asserted low, the chip is initialized and placed in the
reset state. A Schmitt trigger input is used for noise immunity. The
internal reset signal will be deasserted synchronous with the internal
clocks after a fixed number of internal clocks.
Port A GPIO — This GPIO pin can be individually programmed as
an input or open drain output pin. Note that RESET functionality is
disabled in this mode and the chip can only be reset via POR, COP
reset, or software reset.
After reset, the default state is RESET.
GPIOB4
(T0)
(CLKO)
19
Input/
Output
Input/
Output
Input with
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
T0 — Timer, Channel 0
Clock Output — This is a buffered clock signal. Using the
SIM_CLKO Select Register (SIM_CLKOSR), this pin can be
programmed as any of the following: disabled (logic 0), CLK_MSTR
(system clock), IPBus clock, or oscillator output. See Section 6.3.7.
After reset, the default state is GPIOB4. The alternative peripheral
functionality is controlled via the SIM. See Section 6.3.8.
Return to Table 2-2
Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued)
Signal
Name
LQFP
Pin No.
Type
State During
Reset
Signal Description
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